# Logisim Evolution, Grading, and Debugging Need a reminder on how...

## Question

Need a reminder on how to download Logisim Evolution, how your circuits are autograded, or how to debug your circuits? Check the relevant sections of the `Lab 1 document`_.

Constraints
For these problems, unless specified otherwise, you must use designs relying on only the following:

• basic gates (NOT, AND, OR, NAND, NOR, XOR, XNOR) • MUXes
• decoders
• the Logisim Evolution wiring library

Violating specified constraints will result in a 0 on the problem in question. While the autograder may give you credit even if you violate a constraint, we will check submissions after the due date and update grades appropriately. Note that for this lab you may not be warned of all of the autograder's grading criteria. Please read the instructions carefully and heed all constraints.

Logisim Evolution Problems [100]
1. Bit counting [10]

• Submission file for this part: 1.circ
• Main circuit name: bitcounting
• Input pin(s): twelvebitinput [12]
• Output pin(s): zeroes [4]

Suppose we want to determine how many of the bits in a twelve-bit unsigned number are equal to zero.

Implement the simplest circuit that can accomplish this task.

You may use any Logisim Evolution component for this problem except for the "bit adder." Note, however, your design must be combinational, you may not use any clocking or sequential solution.

2. Comparator implementation [20]

• Submission file for this part: 2.circ
• Main circuit name: comparison
• Input pin(s): inputa [2], inputb [2]
• Output pin(s): areequal [1], greaterthan [1], lessthan [1]

Implement a 2-bit comparator.

Note that for greaterthan and lessthan, this means a>b, and a<b respectively. While already specified above, you may not use anything from the Arithmetic library for this problem as this defeats the purpose of the problem. Further, you may only use NAND gates to construct this circuit. I recommend doing the design first with standard gates (on paper) and then converting the design to NAND gates. For this problem your circuit must be minimal and efficient. I encourage you to think carefully about what is needed here. You must use kmaps to implement the basic comparison operations efficiently and you must also think about efficiency with respect to the whole circuit. Your goal will be to construct this circuit with the fewest number of NAND gates possible.

You must implement your comparator within the constraints specified for this lab.

3. Parity checker [5]

• Submission file for this part: 3.circ
• Main circuit name: parity
• Input pin(s): tenbitinput [10]
• Output pin(s): evenparity [11]

Implement a simple even parity checker. Given a ten-bit number, output an 11th bit that ensures the total number of bits that are 1 is even. Concatenate this bit to the original number as the least significant bit.

There are parity gates for both type of parity. It defeats the purpose of this problem if you use those, so you may not use either of them. That said, it's possible to finish this problem using only a single gate.

• Submission file for this part: 4.circ
• Main circuit name: cla
• Input pin(s): inputa [6], inputb [6], carryin [1]
• Output pin(s): carryout [6], generator [6], propagator [6]

Implement a 6-bit carry-lookahead unit (CLA). For the given carryin and each bit of the given inputs inputa and inputb, generate the relevant carryout bits. You will also need to output the corresponding generator and propagator bits.

Your CLA must be a true CLA. If your unit ripples the carry rather than calculating each carry based on the generator and propagator bits, you will get a 0. Your equations for C6 .. C1 should purely be in terms of C0, or carryin. (Note: In class we called carry in C-1, but that presents issues with logisim, so we use C0 here.) If a wire is feeding from your calculated C1 into your calculations for C2, or if you're duplicating the gates for C1 for use in C2, you're making a ripple-carry adder.

While already specified above, you may not use anything from the Arithmetic library for this problem.

5. 12-bit ALU [40]

• Submission file for this part: 5.circ • Main circuit name: alu
• Input pin(s): inputa [12], inputb [12], operation [3]
• Output pin(s): aluout [12], overflow [1], carry [1], zero [1]

I highly recommend that you finish the previous problem before starting this one.

Design a 12-bit ALU. Given the following input as the operation line, each bit cell of the ALU should perform the appropriate operation:

• 000 = AND
• 001 = OR
• 010 = XOR
• 011 = NOT A
• 100 = ADD (A + B) • 101 = SUB (A - B) • 110 = INC A
• 111 = DEC A

All arithmetic operations will be on 2's complement numbers. This only matters for the ADD/SUB/INC/DEC operations, since the others are performed bitwise. Note that you must use your six bit adder from the previous exercise to construct the 12 bit adder/subtractor for this exercise. Your 12 bit adder subtractor must be a "hybrid" circuit such that you make use of two 6 bit CLA units and combine them use ripple carry from one circuit into the other. If you create a pure ripple-carry adder instead of using your previous circuit, you will lose points.

Overflows are expected and you must indicate overflow by properly setting the overflow output bit for operations where overflow can occur. Similarly, you must set the carry output bit whenever the function has the potential to generate a carry. You do not have to do anything special in terms of interpreting carry for subtract operations, just make sure that the carry bit reflects the state of the ALU's carry bit when appropriate. Make sure that the carry bit is not set for operations that do not generate a carry. You must set the zero output bit whenever the result of an operation is equal to zero. This must work for all operations where it is appropriate.

The basic design of this ALU should be bit-parallel, that is, you will create bit-serial modules and combine them in a bit-parallel datapath. To be clear, you will have a 12 bit adder/subtractor and 12 bit logic modules. You must use a 12 bit MUX to route the outputs of these modules.

Your NOT inplementation must make use of the XOR logic circuit and your INC/DEC operations must make use of ADD/SUB. Thus your output MUX will only have four (12 bit) inputs, AND, OR, XOR, and ADD/SUB. This adds complexity to your mapper and various control circuits, but that is the point of this exercise. You will lose points if you do not heed these instructions.

I highly recommend the use of subcircuits to aid in testing and debugging. Create your 12 bit adder, then an adder subtractor, the logic circuits AND, OR, XOR, then combine these to make your ALU.

Note: your controller circuits must be minimal and efficient. You should use kmaps to make sure that this is the case. You will lose points if you attempt to brute force the controllers.

## Solution Preview

These solutions may offer step-by-step problem-solving explanations or good writing examples that include modern styles of formatting and construction of bibliographies out of text citations and references. Students may use these solutions for personal skill-building and practice. Unethical use is strictly forbidden.

<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<project source="2.15.0" version="1.0">
This file is intended to be loaded by Logisim-evolution (https://github.com/reds-heig/logisim-evolution).

<lib desc="#Wiring" name="0">
<tool name="Splitter">
<a name="facing" val="west"/>
</tool>
</lib>
<lib desc="#Gates" name="1"/>
<lib desc="#Plexers" name="2">
<tool name="Multiplexer">
<a name="enable" val="false"/>
</tool>
<tool name="Demultiplexer">
<a name="enable" val="false"/>
</tool>
</lib>
<lib desc="#Arithmetic" name="3"/>
<lib desc="#Memory" name="4">
<tool name="ROM">
0
</a>
</tool>
</lib>
<lib desc="#I/O" name="5"/>
<lib desc="#TTL" name="6"/>
<lib desc="#HDL-IP" name="7">
<tool name="VHDL Entity">
<a name="content">--------------------------------------------------------------------------------
-- HEIG-VD, institute REDS, 1400 Yverdon-les-Bains
-- Project :
-- File    :
-- Autor   :
-- Date    :
--
--------------------------------------------------------------------------------
-- Description :
--
--------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
--use ieee.numeric_std.all;

entity VHDL_Component is
port(
------------------------------------------------------------------------------
--Insert input ports below
horloge_i : in std_logic;                   -- input bit example
val_i      : in std_logic_vector(3 downto 0); -- input vector example
------------------------------------------------------------------------------
--Insert output ports below
max_o      : out std_logic;                   -- output bit example
cpt_o      : out std_logic_vector(3 downto 0) -- output vector example
);
end VHDL_Component;

--------------------------------------------------------------------------------
architecture type_architecture of VHDL_Component is

begin

end type_architecture;
</a>
</tool>
</lib>
<lib desc="#TCL" name="8">
<tool name="TclGeneric">
<a name="content">library ieee;
use ieee.std_logic_1164.all;

entity TCL_Generic is
port(
--Insert input ports below
horloge_i : in std_logic;                   -- input bit example
val_i      : in std_logic_vector(3 downto 0); -- input vector example

--Insert output ports below
max_o      : out std_logic;                   -- output bit example
cpt_o      : out std_logic_Vector(3 downto 0) -- output vector example
);
end TCL_Generic;
</a>
</tool>
</lib>
<lib desc="#Base" name="9">
<tool name="Text Tool">
<a name="text" val=""/>
<a name="font" val="SansSerif plain 12"/>
<a name="halign" val="center"/>
<a name="valign" val="base"/>
</tool>
</lib>
<lib desc="#BFH-Praktika" name="10"/>
<lib desc="#Logisim ITA components" name="11"/>
<lib desc="file#4.circ" name="12"/>
<main name="alu"/>
<options>
<a name="gateUndefined" val="ignore"/>
<a name="simlimit" val="1000"/>
<a name="simrand" val="0"/>
<a name="tickmain" val="half_period"/>
</options>
<mappings>
<tool lib="9" map="Ctrl Button1" name="Menu Tool"/>
</mappings>
<toolbar>
<tool lib="9" name="Poke Tool"/>
<tool lib="9" name="Edit Tool"/>
<tool lib="9" name="Text Tool">
<a name="text" val=""/>
<a name="font" val="SansSerif plain 12"/>
<a name="halign" val="center"/>
<a name="valign" val="base"/>
</tool>
<sep/>
<tool lib="0" name="Pin"/>
<tool lib="0" name="Pin">
<a name="facing" val="west"/>
<a name="output" val="true"/>
</tool>
<tool lib="1" name="NOT Gate"/>
<tool lib="1" name="AND Gate"/>
<tool lib="1" name="OR Gate"/>
</toolbar>
<circuit name="alu">
<a name="circuit" val="alu"/>
<a name="clabel" val=""/>
<a name="clabelup" val="east"/>
<a name="clabelfont" val="SansSerif bold 16"/>
<a name="circuitnamedbox" val="true"/>
<a name="circuitnamedboxfixedsize" val="true"/>
<a name="circuitvhdlpath" val=""/>
<wire from="(510,1690)" to="(630,1690)"/>
<wire from="(570,1450)" to="(570,1460)"/>
<wire from="(870,870)" to="(920,870)"/>
<wire from="(990,510)" to="(990,520)"/>
<wire from="(570,860)" to="(750,860)"/>
<wire from="(450,380)" to="(770,380)"/>
<wire from="(480,1130)" to="(850,1130)"/>
<wire from="(960,550)" to="(1020,550)"/>
<wire from="(840,920)" to="(940,920)"/>
<wire from="(650,820)" to="(690,820)"/>
<wire from="(650,1140)" to="(690,1140)"/>
<wire from="(530,1570)" to="(630,1570)"/>
<wire from="(820,610)" to="(820,1720)"/>
<wire from="(500,980)" to="(500,1020)"/>
<wire from="(530,1570)" to="(530,1610)"/>
<wire from="(480,810)" to="(570,810)"/>
<wire from="(790,640)" to="(790,1390)"/>
<wire from="(240,1780)" to="(270,1780)"/>
<wire from="(1060,380)" to="(1070,380)"/>
<wire from="(710,740)" to="(730,740)"/>
<wire from="(710,1060)" to="(730,1060)"/>
<wire from="(250,1800)" to="(270,1800)"/>
<wire from="(690,1670)" to="(720,1670)"/>
<wire from="(240,640)" to="(240,680)"/>
<wire from="(570,1790)" to="(600,1790)"/>
<wire from="(240,960)" to="(240,1000)"/>
<wire from="(160,910)" to="(160,1020)"/>
<wire from="(160,910)" to="(180,910)"/>
<wire from="(500,660)" to="(500,700)"/>
<wire from="(220,1290)" to="(240,1290)"/>
<wire from="(570,1640)" to="(570,1760)"/>
<wire from="(260,1820)" to="(270,1820)"/>
<wire from="(940,490)" to="(1010,490)"/>
<wire from="(280,1320)" to="(280,1380)"/>
<wire from="(490,1800)" to="(890,1800)"/>
<wire from="(570,810)" to="(570,860)"/>
<wire from="(940,480)" to="(1020,480)"/>
<wire from="(750,840)" to="(890,840)"/>
<wire from="(690,820)" to="(690,830)"/>
<wire from="(970,540)" to="(1020,540)"/>
<wire from="(940,510)" to="(990,510)"/>
<wire from="(690,1140)" to="(690,1150)"/>
<wire from="(490,1820)" to="(490,1830)"/>
<wire from="(790,520)" to="(840,520)"/>
<wire from="(850,860)" to="(850,1130)"/>
<wire from="(940,500)" to="(1000,500)"/>
<wire from="(300,1710)" to="(300,1720)"/>
<wire from="(160,360)" to="(270,360)"/>
<wire from="(230,1560)" to="(230,1580)"/>
<wire from="(480,840)" to="(590,840)"/>
<wire from="(480,1160)" to="(590,1160)"/>
<wire from="(890,880)" to="(890,1800)"/>
<wire from="(870,870)" to="(870,1470)"/>
<wire from="(180,300)" to="(180,640)"/>
<wire from="(160,360)" to="(160,700)"/>
<wire from="(940,520)" to="(980,520)"/>
<wire from="(1040,850)" to="(1040,860)"/>
<wire from="(530,1300)" to="(530,1320)"/>
<wire from="(210,680)" to="(240,680)"/>
<wire from="(210,1000)" to="(240,1000)"/>
<wire from="(940,540)" to="(960,540)"/>
<wire from="(530,1650)" to="(550,1650)"/>
<wire from="(490,640)" to="(520,640)"/>
<wire from="(490,960)" to="(520,960)"/>
<wire from="(140,860)" to="(140,960)"/>
<wire from="(700,1820)" to="(720,1820)"/>
<wire from="(260,1300)" to="(280,1300)"/>
<wire from="(370,370)" to="(390,370)"/>
<wire from="(170,780)" to="(170,820)"/>
<wire from="(500,1610)" to="(530,1610)"/>
<wire from="(940,530)" to="(970,530)"/>
<wire from="(760,1390)" to="(790,1390)"/>
<wire from="(890,880)" to="(920,880)"/>
<wire from="(490,660)" to="(500,660)"/>
<wire from="(490,980)" to="(500,980)"/>
<wire from="(120,1630)" to="(200,1630)"/>
<wire from="(480,790)" to="(560,790)"/>
<wire from="(710,680)" to="(710,740)"/>
<wire from="(480,1110)" to="(560,1110)"/>
<wire from="(710,1000)" to="(710,1060)"/>
<wire from="(190,700)" to="(190,880)"/>
<wire from="(260,1430)" to="(260,1490)"/>
<wire from="(940,450)" to="(1020,450)"/>
<wire from="(890,410)" to="(890,550)"/>
<wire from="(980,520)" to="(980,530)"/>
<wire from="(990,850)" to="(990,860)"/>
<wire from="(210,620)" to="(270,620)"/>
<wire from="(210,940)" to="(270,940)"/>
<wire from="(120,780)" to="(120,1300)"/>
<wire from="(140,960)" to="(190,960)"/>
<wire from="(120,780)" to="(170,780)"/>
<wire from="(490,1470)" to="(870,1470)"/>
<wire from="(250,770)" to="(560,770)"/>
<wire from="(250,1090)" to="(560,1090)"/>
<wire from="(660,1810)" to="(700,1810)"/>
<wire from="(980,530)" to="(1020,530)"/>
<wire from="(630,1240)" to="(630,1320)"/>
<wire from="(360,300)" to="(360,330)"/>
<wire from="(220,810)" to="(260,810)"/>
<wire from="(220,1130)" to="(260,1130)"/>
<wire from="(720,1410)" to="(720,1490)"/>
<wire from="(890,410)" to="(1060,410)"/>
<wire from="(510,1650)" to="(510,1690)"/>
<wire from="(230,630)" to="(230,790)"/>
<wire from="(230,950)" to="(230,1110)"/>
<wire from="(1070,490)" to="(1080,490)"/>
<wire from="(720,1410)" to="(740,1410)"/>
<wire from="(720,1730)" to="(740,1730)"/>
<wire from="(270,720)" to="(290,720)"/>
<wire from="(270,1040)" to="(290,1040)"/>
<wire from="(760,640)" to="(790,640)"/>
<wire from="(890,850)" to="(920,850)"/...

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