1) Examine the 4-bit Synchronous Up/Down Counter on Slide 12 from Module 5, Topic 2 Counters Lecture notes. Convince yourself that it works. Using the Sequential Circuit Design Procedure, build a 3-bit Synchronous Up/Down Counter using D flip-flops. The up/down control can be thought of as an external input (call it x). Show your State Table, K-Maps, and properly formatted circuit diagram.
2) Build a 3-bit synchronous rotate left register using a T flip-flop for the most significant bit, a D flip-flop for the middle bit, and a T flip-flop for the least significant bit. Asynchronous rotate left register will rotate all the bits left one position with the most significant bit copied to the least significant bit. Show your State Table, K-Maps, and properly formatted circuit diagram.
3) Build a synchronous circuit to decrypt passwords. Let us assume that: passwords are 3 bits inside and an encrypted password is the original password plus 1 and rotated once to the right (e.g. if the password is 000, we add 1 to give us 001, and then rotate right, which gives the encrypted password as 100). Design and build (with D flip-flops) the sequential circuit to decrypt the password (perform the encryption process in reverse rotate left one bit first, and then subtract 1). Show your State Table, K-Maps, and properly formatted circuit diagram.
4) Build a 3-bit Asynchronous Up Ripple Counter similar to the 4-bit version on Slide 7 from the Module 5, Topic 2 Counters Lecture notes (add a Clear control signal to quickly reset the counter). Make sure that each D flip-flop (D2-D2) is Positive (Rising-) Edge triggered. Show your properly formatted circuit diagram.
(a) Starting with 000, what are the values of Qo Q2 as your clock cycles (show the table)?
(b) Reset the counter to 00 Jand then change all the D flip-flops so they are Negative-(Falling-) Edge triggered. What are the values of Qo Q as your clock cycles (show the table)?
(c) Reset the counter to 000 and then change the Do and D2 flip-flops so they are Positive-edge triggered (D1 is Negative-edge triggered). What are the values of Qo Q2 as your clock cycles (show the table)?
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