## Transcribed Text

A1 (5 marks)
(a)
For the circuit shown in figure Q1, calculate both the current and power dissipated in
each resistor and the diode. State which diode model you use.
(3 marks)
4.7kQ
6V
R1
D1
R2
2.1kQ
Figure Q1
(b)
If the power dissipated by the diode in figure 6(a) must be restricted to 0.25 mW,
calculate
(i)
A new value of R2 to achieve this leaving R1 unchanged.
(ii)
A new value of R1 to achieve this leaving R2 unchanged.
In each case state whether the resistance value calculated is the maximum or
minimum allowable.
(2 marks)
A2 (5 marks)
Use Boolean Algebra (i.e. do not use a Karnaugh Map) to derive the minimum form of the
following two expressions:
(i)
F = A. B + C. (B + C)
(2 marks)
(ii)
F = A. B. C + A. B. C + A. B. C + A. B. C + A. B.C
(3 marks)
A3 (5 marks)
Figure Q3 shows a circuit constructed of logic gates with two inputs A and B.
(a)
Write down the logic functions at the output of each gate.
(2 marks)
(b)
Hence use Boolean Algebra to show that the circuit implements an exclusive OR
(EXOR) function.
(3 marks)
A
F
B
Figure Q3
A4 (5 marks)
Figure Q4 shows the logic diagram for a clocked D-type flip flop comprising NAND gates.
characteristic equation for the Q output (you may find it helpful to use
2 of 2
diate gate outputs X and Y).
(2 marks)
racteristic equation to derive the flip-flop next state table for all
ns of the inputs.
(3 marks)
D
X
Q
C
Q
Y
Figure Q4
B1 (20 marks)
A logic function Fis represented by the following sum of products (SOP) expression:
F FA B, C, D) = (0, 3, 5, 6, 7, 12, 13, 14, 15).
(a)
Draw a Karnaugh Map for four variables and label each square with the correct
minterm number.
(3 marks)
(b)
Hence, use a Karnaugh Map to reduce the expression to the minimum SOP form.
(7 marks)
(c)
Draw the logic circuit that results from part b) above.
(4 marks)
(d)
Use Boolean algebra to convert the expression you obtained in part b) above to one
suitable for implementation using NAND gates only and draw the resulting NAND
gate circuit.
(6 marks)

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