Design a synchronous counter to produce the following binary sequence. Use J-K flip-flops and other gates necessary:1 – 4 – 3 – 5 – 7 – 6 – 2 – 1 – 4 – .......
1.Design: draft the specification for the counter including the inputs and outputs. Construct state tables based on your specification, and use the K-map if necessary to optimize your functions for the outputs. Include the specification, input/output definitions, state tables, and the K-maps in your lab report.
2.Create a new design file, in this design file, draw the circuit you have designed from step 1. You may use SPDT switches to provide control inputs. You may use LED arrays to show your binary sequence or use a 7-segment display to display the binary sequence in a human readable manner.
3.Run simulations to test your design. You should verify that the counter you design generates the correct sequence. Capture a series of screenshots to demonstrate the correct sequence generated by your counter and include a short explanation on how you can conclude that your circuit is functioning correctly.

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