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Digital Logic Design Mini-Project Description In this assignment, you are required to design a simple digital system that is composed of a combinational logic circuit (CLC) and a synchronous sequential logic circuit (SLC) as shown in Figure 1. Input Clock SLC CLC LEDs to Display Count LEDs to Display Remminder Figure 1. Block diagram of the system. The SLC is basically a counter built using JK flip-flops that behaves based on an external input. The count value should be displayed on light emitting diodes (LEDs) and is also the input to the CLC component. The behavior of the counter to be designed depends on the least significant digits of your university ID; specifically, the ones and tens digits. Table 1 lists the behavior of the counter to be designed based on these two numbers. For example, if your ID is 2018xx34, then you should design counter number III since the ones digit is even and the tens digit is odd. So, you need to design one counter only based on your ID. The CLC is supposed to calculate the remainder of dividing the count value by some value R which is specified as follows: the ones digit in your ID if it is between 2 and 5 R your section number otherwise The output of the CLC is also shown on LEDs. Table I. Counter Behavior based on the Last Two Digits of Student ID Tens Ones Counter External Counter Behavior Digit Digit Number Input 0, 3, 2, 6, 4, 1, 5, 7, 0,3, 2, 6, 4, 1, 5, 7, Even Even I 1 Counter pauses at the current count 0, 5, 2, 4, 6, 1, 3, 7, 0, 5, 2, 4, 6, 1, 3, 7, Even Odd II 1 0, 7,3,1,6,4,2,5,0,7,3,1,6,4,2, 5 Counter pauses at the current count Odd Even III 1 0, 7, 5, 1, 4, 6, 2, 3, 0, 7, 5, 1, 4, 6, 2, 3, Odd Odd 0, 2, 4, 6, 7, 5, 3, 1, 0, 2, 4, 6, 7, 5, 3, 1, ... IV 1 0, 1, 3, 5, 7, 6, 4, 2, 0, 1, 3, 5, 7, 6, 4, 2, ...

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