Part 1: Creating a Stimulus File.
1. Read Creating your Stimulus File.pdf (available on Canvas). Don’t do any of the steps yet,
just read through the document.
2. Create a stimulus file for lab2.
You will need at least 3 inputs (x, y, z). Start with a clock frequency of 1khz and double
it successively for each remaining input. You should end up with signals of 1khz, 2kz, and 4khz.
Note that you will need to add an input to this file for the last portion of the lab.
Part 2: Design
Note that for this lab, each design step requires you to add a schematic to your design. You do
this by right-clicking on the .dsn and selecting New Schematic. Remember to rename your
schematic to something appropriate for this lab. Ex. Lab2_1. You will have to add a page to
the newly created schematic. Right-click on the schematic and make the appropriate selection.
You need to rename your new page as well. Before simulating the new schematic/design you
will need to make it root. Right click on the schematic and select make root. Don’t forget to do
this each time you wish to simulate a new design. For a pspice simulation profile to run, the
desired schematic MUST be the root.
For each design you should be sure to create the most optimized circuit you can. This means
you may have to do some algebraic manipulation.
1. Read Extension of Multiple Inputs (pg 62), if you haven’t already.
2. Simulate both sides of the function in 2.1a from the book. You will need to create a
schematic page for both the left hand side and right hand side of the two expressions. Create a
simulation profile for this schematic. Use your newly created input file.
3. Add a new schematic to your project. You will have to add new pages to your schematic to
prove via simulation that 2.1 b is true. Remember to add a page for the left hand side and one
for the right hand side. You will have to create a new simulation profile for this schematic and
ensure that the schematic is root before you will be able to successfully run the simulation.
4. Add a new schematic to your project. Create a 3 input OR-gate. DO NOT USE THE ONE IN
ORCAD. You will have to create a 3-input truth table, create the expression, simplify if possible.
Create a design and simulate it.
Part 1: Adders
1. Open a new project called Adders. Rename the Page and the Schematic
“Half_Adder.” This is an important step, don’t skip it.
2. Create your half-adder. Name the upper input “X” and the lower input “Y.”
The outputs should be named “SUM” and “CARRY.” IMPORTANT: Use XOR 7486
3. Place the ports. DO NOT use DSTIM1 as the inputs for x and y. Use
PORTRIGHT-R. This port can be found in the same place as PORTLEFT-L. This is
because you will be creating a user-defined part for the half adder later on. If you
do use a DSTM1 input at this point you WILL create a problem which will
require you to start this part of the lab over.
4. SAVE YOUR DESIGN.
Creating a part.
You can generate a part for any circuit design you create. This increases the
flexibility of the software and the simplicity of designs.
To generate a part from your design, complete the following steps.
1. In the Project Manager window (this is the hierarchical view of your project),
select the Half_Adder folder.
2. From the Tools Menu, (top menu bar), select Generate Part.
3. In the Generate Part dialog box which appears, specify the location
(Netlist/source file) of the design file that contains the circuit for which the part is
to be made – adders.dsn. It may or may not be filled in for you.
4. In the Netlist/source file type drop-down box, specify the source type as
5. In the Part Name text box, specify Half_Adder.
6. The name and location of the library that will contain the created part is
….\adders.olb. If you are using a flash drive, the path should be changed
7. Save the source schematic by selecting the Copy Schematic to library check
box. This is not checked in the picture above. Be sure you do select it for this
8. Be sure Create new part is selected.
9. To specify the schematic folder that contains the design for which the part is to
be made, select Half_Adder from the Source Schematic name drop-down list box.
Then click Save. You should see something like this.
This is where you can change the location of your ports, if for some reason
Orcad’s part generator doesn’t place your ports where you want them.
Building a Full-Adder
1. In the Project Manager window, right-click on Adders.dsn and select New
Schematic. Name it Full_Adder and click OK.
2. A folder named Full_Adder should appear below the Half-Adder folder.
3. Save the design.
4. Make the full adder circuit design root, or the higher level hierarchical block.
Right click on Full_Adder and select Make Root. The Full_Adder folder moves up
and a forward slash appears in the folder.
5. Right-click on Full_Adder and select New Page, specify the page name as
Full_Adder and click OK. A new page, Full_Adder, gets added below the
schematic folder Full_Adder
6. Open the Full_Adder page you just added to open it for editing.
7. In the place part menu, under libraries click on ADDERS. The part you made
previously should be here.
8. Use the Half_Adder part you created and make a full adder.
9. Place an OR gate (7432) to the schematic. Then add the wires as shown in the
10. At this point you are ready to add the stimulus to the design. Add DigStim1,
from the Part List, to the inputs on the left of the design. Remember to hit escape
11. Change the Implementation Value of the three inputs to Carry_in, X, and Y,
respectively. Carry_in should be the name of the top-most input.
12. Select the Place Port button and add a port (PORTLEFT-L) to the output
of the OR gate. Change the port name to CARRY_OUT. Also add a port for the
SUM and rename it appropriately.
13. Save the design.
Annotate the design
This is different than what you have done previously so carefully follow all steps.
The difference is because you are now annotating a design which uses a usercreated
1. In the Project Manager window, select the .dsn file.
2. Choose Tools - Annotate.
3. In the Packaging tab of the Annotate dialog box, specify whether you want the
complete design or only a part of the design to be updated. Select the Update
entire design option.
4. In the Actions section, select the Incremental reference update option.
5. Select the Update Occurrences option.
Note: When you select the Update Occurrences option, you may receive a
warning message. Ignore this message because for all complex hierarchical
designs, the occurrence mode is the preferred mode. The Use instances option is
shown as preferred because the project type is Analog or Mixed A/D.
6. For the rest of the options, accept default values and click OK to save your
The Undo Warning message box appears.
7. Click Yes.
A message box stating that the annotation will be done appears.
8. Click OK.
Your design is annotated and saved. You can view the value of updated cross
reference designators on the schematic page.
Please note that each time you make a change to parts/wires/components in a
design you will need to re-annotate the design. If you have used a part you
created you may need to update occurances. You definitely will if you change the
part design and recreate the part.
Test Your Full Adder
1. To test your design, you will have to create a stimulus file with 3 inputs. You
will need to ensure that whatever frequencies you select for your inputs, you
cover all the possible combinations of the three inputs. Remember with 3 inputs
there are 2n = 8 possible combinations. It is strongly suggested that with each
input you double the previous frequency to ensure you create all possible
combinations of the inputs.
2. Once you have created your stimulus file, simulate your design.
Build a 2 bit adder.
1. Create a part for the Full-Adder. You will need to ensure that you replace the
DigiStim inputs on the previous design with ports. If you do not your design will
not work right.
2. Use your newly created part to create a 2 bit adder.
3. Simulate your design using the provided 2BitAdderTest.stl file.
Lab 5 Examining Flip-Flops and Latches
For this lab it is crucial that you put your flip-flop in a known state.
Part 1. – D Latches and Flip-flops
1. Build the D-Flip-flop shown below. Notice there is a reset input on this flip-flop.
2. Create a part for your D-Flip-Flop.
3. It is to your benefit to test your flip-flop before continuing. The results of this simulation will
not be graded, but if your part doesn’t work properly the rest of the lab won’t work properly
Part 2. T and JK from D
1. Build a T and a JK flip-flop from your D-Flip-flop each in its own schematic folder and on its
2. Create parts for each and test appropriately.
Part 3 T and D from JK
1. Using part 74107, build a T and a D-flip. Do NOT put both designs on the same schematic
2. Create parts for each and test appropriately.
Part 4. Mystery Circuit
1. Given the following design.
a. Create a state table
b. Create a state diagram
2. Build the circuit, using your T flip flop from Part 3.
3. Simulate the design.
4. Create a part and name it appropriately
5. Simulate your part.
For this lab you will have to create TWO projects. One where you build and test the
parts and one for the final design. This is necessary to avoid the part limit imposed
on the free version of OrCad®
Part 1. Create a 4 to 1 multiplexer (with an Enable) using ONLY NAND gates.
Create a part for your multiplexer and test it. You will have to create the stimulus
(.stl) file for this simulation.
Parts you may use – 7400 7420. NO OTHER PARTS ARE REQUIRED
Part 2. Create a 3 bit parallel register using a D flip-flop made from a JK. This part
(the D from JK flip-flop) was created in Lab 5. If you did not create the part then,
you will need to do so now. Create a part and test your register. You need to
create the stimulus (.stl) file for this simulation.
Part 3. Create a 3 bit universal shift register. You will need to modify the one
shown in your book to do this. Simulate all the functionality of this register.
Input Table: NOT the same as in the book.
Multiplexer Input Action
1 Integer multiply by 2 (shift left)
2 Integer divide by 2 (shift right)
3 Do nothing
NOTE: You WILL have to create several pSpice simulations to achieve a complete
test. Use the add to profile (not add to design) option to avoid potential conflicts
between your simulation profiles.
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