Cache Design
1) Assume a 256KB cache where the cache block size is 64B. Let A[31:0] be memory addresses from CPU. Show the tag, index, and block offset bits divided from A[31:0] in order to find a cache block correctly if this cache is organized as a) direct-mapped or b) 4-way associative.

2) Assume that the cache hit time is 3ns and the memory access time is 25ns. What is the maximum cache miss rate for the average access time of this cache memory to be no more than 5ns?

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