1 (BF)16 = (10111111)2
2 A CPU that has a split cache can fetch both the instruction and data at the same time.
3 EEPROM is nonvolatile memory.
4 Compiled programs written for CISC processors have a smaller number of instructions than those written for RISC.
5 Instruction Register (IR) holds the address of the next instruction to be executed.
6 Flags register is one of the CPU special purpose registers which holds the status of the last performed instruction.
7 Using two five-stage pipelines will allow CPU to execute two instructions on parallel.
8 In Big-endian system, bytes representing numbers are stored Right-to-Left.
9 X XOR 0 = X' (complement of X)
10 It is possible to implement any combinational circuit using only NOR gates.
These solutions may offer step-by-step problem-solving explanations or good writing examples that include modern styles of formatting and construction of bibliographies out of text citations and references. Students may use these solutions for personal skill-building and practice. Unethical use is strictly forbidden.1) Is true because B=1011 and F=1111 => (BF)16=(10111111)2
2) Is true because in a split cache, the CPU can fetch an instruction and data access at the same time even without a cache, while in unified cache it cannot.
3) True as per theory
4) True because CISC (compiled) programs use less instructions which are more complex than RISC which uses more simpler instructions....
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