3 Questions With DRAM Chip Organization

Q1). Chip size is an important packaging parameter and contributes greatly to system size.
It is largely determined by the number of pins. Assume a memory chip holding 1M bits, with non-multiplexed address and data. How many address and data pins are required when the chip is internally organized as 1Mb x 1 bit, 512 kb x 2 bits, 256 kb x 4 bits and 128kb x 8 bits?

Q2). Consider a DRAM memory chip organized as 2048 x 2048 array of bits. Assume that each row must be refreshed every 4 msec and that each refresh requires 50 nsec.
What percentage of time is spent on refresh?

Q3). Figure 5.6 indicates how to construct a module of chips that can store 1 MByte based on a group of four 256-Kbyte chips. Let’s say this module of chips is packaged as a single 1-Mbyte chip, where the word size is 1 byte. Give a high-level chip diagram of how to construct an 8-Mbyte computer memory using eight 1-Mbyte chips. Be sure to show the address lines in your diagram and what the address lines are used for.

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