QuestionQuestion

Instructions: Answer each question IN YOUR OWN WORDS. Place the answers directly under each question (i.e. do not delete the questions).

Pipelining

1. Answer the following questions about a pipelined MIPS datapath, using this instruction sequence:
sub    $8, $9, $10
add    $12, $13, $8
or    $11, $10, $9
and    $15, $8, $12
sw    $12, 4($11)

a. Identify all of the data dependencies, in the above instruction sequence, which will require forwarding. For each time a value will require forwarding, state:
• which register value will need to be forwarded
• what instruction the value will be forwarded from
• what instruction the value will be forwarded to .

b. For each item that requires forwarding from part (a), explain:

i.   When the item will be forwarded (i.e. during what cycle, assuming that the SUB instruction begins in cycle 1)
ii. Which pipeline register the item will be forwarded from
iii. Which hazard detection rule was used to detect the hazard (give entire rule).

2. A branch instruction can cause pipeline flushing to occur.

Assume the standard 5-stage MIPS pipeline, with no branch hazard reduction techniques implemented, is being used on this code:

lw    $8, 100($0)
next: sub    $10, $10, $12
addi   $8, $8, -10
or    $13, $9, $13
slti   $11, $8, 40
beq    $11, $0, next
add    $14, $15, $16
andi   $10, $9, 55

a. For the above code, explain the situation in which the pipeline would NOT need to be flushed. Include in your explanation:

i) If the LW instruction starts in cycle 1, in which cycle will the branch be evaluated?
ii) What instructions will be in the pipeline, at which stages, when the branch is being evaluated?
iii) What kind of value would need to be loaded into register $8 by the first instruction, so that a pipeline flush would NOT be needed?
Explain why the flush would NOT be necessary.

b. This time, again using the above code, explain the situation in which the pipeline WILL need to be flushed. Include in your explanation:

i) What kind of value would need to be loaded into register $8 by the first instruction to cause a pipeline flush the first time this code runs?
Explain why the flush WOULD be necessary
ii) Which instructions would need to be flushed when this happens?

3. Structural, data, and control hazards typically require a processor pipeline to stall.

Listed below are a series of optimization techniques implemented in a compiler or a processor pipeline designed to reduce or eliminate stalls due to these hazards.
Answer the questions for each of the following optimization techniques.

a. Branch Delay Slots

i. Which type of pipeline hazards does this technique address, and how?
ii. Explain how the code segment in question 2 could be re-arranged to implement “branch delay slots", and eliminate the branch delays due to stalling.
Assume with no branch hazard reduction techniques have been implemented.

b. Branch Prediction

i. Which type of pipeline hazards does this technique address, and how?
ii. Which type of branch prediction would best reduce the branch delays in the specific code segment from question 2? Explain.
iii. Would any delays still remain in the code segment from question 2, when using this type of branch prediction? Explain.

c. Adding additional duplicate functional units (ALUs, adders etc)

i. Which type of pipeline hazards does this technique address, and how?
ii. Give an example.

Caches

4. Consider the following two different types of cache design, BOTH for a cache whose total cache data size is 40 words:

a. Cache Design #1: Direct mapped cache with 8-word blocks

For design 1, how many cache indexes will this cache have and how many words will be loaded on a miss?

b. Cache Design #2: Two-way set associative cache with 5-word blocks

For design 2, how many caches sets will there be? How many lines will be in each set? How many words will be loaded on a miss?

For each of the above designs for a 40-word cache, explain what happens when you access five memory words, as listed below (words accessed are different for each design). NOTE: You may use a table, as long as all items are addressed.

c. Explain how Design 1 (direct mapped cache with 8-word blocks) accesses words 88, 90, 190, 103, 104, in the order listed.

For each word accessed, you must state:
• what memory block the memory word is in
• what cache index the block maps to
• if it is a hit or miss
• for a miss, which words will be loaded, and what block will be overwritten, if any

d. Explain how Design 2 (2-way set associative cache with 5-word blocks)   
    accesses words 89, 90, 31, 94, 25 in the order listed.

Assume an LRU replacement with line 0 containing the LRU block.

For each word accessed, you must state:
• what memory block the memory word is in
• what cache set the block maps to
• if it is a hit or miss
• for a miss: which words will be loaded, and what line within the set the words will be placed into
• any re-arranging of the cache that is needed to keep track of the LRU

Input/Output

5. Give a concise answer to each of the following questions.
a. How does interrupt-driven IO work?
b. Why is DMA an improvement over interrupt-driven I/O?
c. Would DMA transfer ever be a poor choice?

6. Compare and contrast distributed arbitration by self-selection vs
arbitration by collision detection.
a. How does arbitration by self-selection work?
b. How does arbitration by collision detection work?
c. Explain when arbitration by self-selection would be most appropriate vs. when arbitration by collision detection would be most appropriate.

7. Name one advantage and one disadvantage of using a single bus as
a shared communication link between memory, processor and I/O devices.

a. Advantage?
b. Disadvantage?

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