The following is needed for VHDL to be compiled in ModelSim:
Make a counter, count till 255 --> then back,
When count = 0 - 127, write <= '1';
Otherwise write '0'
When count = 128 - 255, read <= '1'
else read <= '0'
Also, add two output ports for read/write and generate address by incrementing the counter.
Subject
Computer Science Verilog, VHDL
Question
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module Counter( Clk, Reset, Rd, Wr);
input Clk;
input Reset;
output reg Rd;
output reg Wr;
reg [7:0] counter;...
input Clk;
input Reset;
output reg Rd;
output reg Wr;
reg [7:0] counter;...
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