Implement the adder in Verilog. Use either structural or behavioral or any combination for level 1, you can re0-use existing implementation from the literature for this level.
For level 2, you have implement a structural module identical.
Write a test bench to test it for all different values including this: 0, minimum, maximum, positive, negative (25 different combinations).
Show snapshot of simulation in a document and submit it along with Verilog Module.
1-level Carry-Select Adder (CSA)
Conditional sum adder (SUM)
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//assuming carry in 0
//assuming carry in 1
//select either carry 1 or 0 using carry out of FA...
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