Implementation of Adder in Verilog

Implement the adder in Verilog. Use either structural or behavioral or any combination for level 1, you can re0-use existing implementation from the literature for this level.
For level 2, you have implement a structural module identical.
Write a test bench to test it for all different values including this: 0, minimum, maximum, positive, negative (25 different combinations).
Show snapshot of simulation in a document and submit it along with Verilog Module.
1-level Carry-Select Adder (CSA)
Conditional sum adder (SUM)

module carry_sel(a,b,cin,sum,co);
input [3:0]a;
input [3:0]b;
input cin;
output [3:0]sum;
output co;
wire [3:0]sum;
wire co;

wire s1,c1,s2,c2,s3,c3,s4,s11,s44,c4,c11,s22,c22,s33,c33,c44;
//assuming carry in 0
fulladd x1(a[0],b[0],0,s1,c1);
fulladd x2(a[1],b[1],c1,s2,c2);
fulladd x3(a[2],b[2],c2,s3,c3);
fulladd x4(a[3],b[3],c3,s4,c4);

//assuming carry in 1
fulladd x5(a[0],b[0],1,s11,c11);
fulladd x6(a[1],b[1],c11,s22,c22);
fulladd x7(a[2],b[2],c22,s33,c33);
fulladd x8(a[3],b[3],c33,s44,c44);

//select either carry 1 or 0 using carry out of FA...

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