Question

Check the file: Questions.pdf and solve the task given on page 3.

Solution Preview

This material may consist of step-by-step explanations on how to solve a problem or examples of proper writing, including the use of citations, references, bibliographies, and formatting. This material is made available for the sole purpose of studying and learning - misuse is strictly forbidden.

Basic Functionality
A simple processor has been designed to perform a set of Logic and Arithmetic operations. A hierarchal design with structural VHDL code has been implemented in this experiment. The design is partitioned into smaller hardware blocks.
The top-level design of the processor has following components:
1. Mux
2. 4-bit Registers
3. ALU
4. Flip flop
All these modules use behavioral VHDL code.

The inputs A and B are stored in 4-bit registers.
ALU takes these register outputs and opcode as input. Based on the opcode value, specific operations are performed on A and B by ALU.
Following operations are implemented:
- logical operations (complement, and, or, nor, nand, xor, xnor)
- arithmetic operations (transfer, increment, decrement, add, subtract)
These functions are implemented using a case statement.
The output of ALU can be stored in one (or both) of the 4-bit register, using loadA or loadB input signal. Along with the ALU 4-bit output, Carry-out (Cout) is also generated from ALU....

This is only a preview of the solution. Please use the purchase button to see the entire solution

Assisting Tutor

Related Homework Solutions

Verilog (VHDL) Compiling in ModelSim
Homework Solution
$25.00
Verilog
Computer Science
Programming
ModelSim
Counter
Output Ports
Incrementing
If Statement
Read Command
Write Command
Creating A Calculator Using Verilog
Homework Solution
$60.00
Verilog
Computer Science
Programming
Engineering
16-Bit Numbers
Arithmetic Operations
Decrementation
Incrementation
Output Results
Input Values
Verilog Lab
Homework Solution
$123.00
Computer
Science
Verilog
Lab
Algorithm
Diagram
Division
Simulation
Code
Planning
Implementation of Adder in Verilog
Homework Solution
$50.00
Verilog
Computer Science
Programming
Carry-Select Adder
Conditional Sum Adder
Structural Combination
Behavioral Combination
Simulation
Digital Logic Verilog
Homework Solution
$127.00
Computer
Science
Digital
Logic
Verilog
Input
CPU
Interface
Design
Bit
Output
Get help from a qualified tutor
Live Chats