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Learning objective Use the Spartan 6's embedded Block RAM and the Xilinx Core Generator to implement a data buffer. Introduction Often there is a need to store more data than can reasonably put in a register file. The Xilinx Spartan 6 FPGA on the Nexys3 board contains 32 Block RAMs to help with this problem. Each Block RAM contains 18,432 bits of fast static RAM, 16K bits of which is allocated to data storage and, in some memory configurations, an additional 2K bits allocated to parity or additional "plus" data bits. This lab will use the Block RAM to store data received from the serial interface developed in Lab 5. The data received will be stored in the RAM and upon command (push button switch) the data will be read out and transmitted back to the PC for display in the PuTTy window. The block diagram for the complete system is shown below. Clock lines and are not shown for simplicity. Port A: Write Port B: Read 8 TXD dina doutb 8 8 SerialRx rx_done_tick BRAM addra Addr Gen addrb 8 wea RXD SerialTx control / tx_start_tick status signals 1 switch LED CONTROLLER inputs outputs Physically, the block RAM memory has two completely independent access ports, labeled Port A and Port B. The structure is fully symmetrical, and both ports are interchangeable and both ports support data read and write operations. In this lab we will be using the block RAM as a simple dual port RAM. Simple Dual-Port RAM DINA ADDRA WEA SBITERR ENA DBITERR CLKA RDADDRECC INJECTSBITERR INJECTDBITERR ADDRB DOUTB ENB RSTB REGCEB CLKB Figure 21: Simple Dual-port RAM Port A is the write port, and Port B is the read port. Reads and writes are synchronous, and can potentially be performed with different clocks; here, CLKA and CLKB will be connected to the master clock. The write port has a write enable (WEA); we will not use the optional clock enables ENA and ENB. Here are the specifications for the system: The system stores up to 32 8-bit ASCII characters in BRAM. The rx_done_tick signals the memory controller to store the received character in the BRAM. The received characters are simultaneously echoed back to the serial transmitter. If the memory fills up (32 characters stored), an LED lights and no further characters are stored or echoed back to PuTTy. Pushing a button causes the memory to be emptied, sending the characters in sequence to the serial transmitter, beginning with the first character entered. (You will now see the characters a second time on the PuTTy window.) If you typed in 10 characters, then 10 characters are sent back. You don't dump the entire memory back to the transmitter. After sending the stored characters back, the memory controller is reset so that new data can be stored. A second LED lights indicating that the memory is "empty". It isn't really empty, though - the characters you typed are still in there, but the write address is reset to zero so that the next time you type, the old characters will be overwritten. (This is, by the way, how files are deleted on your computer. Unless you take special measures to erase the storage, the file's data are still there. All that is actually removed is the file systems's pointer to the file.) The SerialRx and SerialTx blocks are the same ones you used in Lab 5. What you will add in this lab are the items inside the dashed box: BRAM, address generator, controller, and multiplexer. BEFORE COMING TO LAB Part I: Prelab 1. Generate Block RAM with the core generator (a) Create a new project (i.e., lab6_mem_your initials) and add the source code from your Lab 5 serial interface. (b) Start the core generator from ISE: Project > New source The New Source wizard should appear. Select IP(Core Generator and Architecture Wizard), give your new BRAM a file name, check the Add to Project box, and click Next. Lab 5: Memory View by function tab and expand Memory and storage elements, then RAMs and ROMs and finally Block Memory Generator. You now need to tell the core generator all of the parameters of the memory you want it to create. On page 1 choose Native. On pages 2 & 3 choose Simple dual-port RAM and Minimum area. The write width will be 8 and depth will be 32. The operating mode is Write-first and the outputs are Always enabled. The read width will be 8. Choose the defaults through the rest of the set-up. On the last page (page 6) click Generate. Wait for the core generator, it could take several minutes. There will be several outputs from the core Generator: .xco file inserted into the project vhd file in the ipcore_dir folder in your project folder (wrapper for functional simulation) vho file in the ipcore_dir folder in your project folder (instantiation template for structural VHDL top level) Various other lower level files (e.g., ingc) in the the ipcore_dir folder in your project folder. The .xco file contains pointers to the generic, parameterized HDL models in the XilinxCoreLib libraries. The vhd file describes the behavior of the Block RAM and is only used for the simulation. The instantiation template (.vho file) contains instructions describing how the core is instantiated into the design. During design implementation the Xilinx tools merge the core's .ngc netlist with the rest of the design. Generate Core EDN .xco VHO .VHD Instantiate Simulate Implement 2. Instantiating Cores in a VHDL Design. Copy the component declaration and the instantiation from the core's instantiation template (.vho file) into the appropriate areas of your Lab 6 top level file. Change your_instance_name (a dummy name from the instantiation template) to the actual instance name you want to use, and modify the port connections copied from the instantiation template to reflect the actual connections. 3. Add the memory controller to your top level design. Add a debouncer to the pushbutton switch input (downloaded previously from Canvas). You may also need to add a monopulser state machine so that you only trigger the readback once with each button press, not multiple times. 4. Write a testbench (a modification of the SerialRx testbench from Lab 5) that simulates using the block RAM to store received characters, then read back and transmit them through the serial link back to the computer. Remember that your design should remember the last address written and only read back the amount data that was stored. When you get the simulation working, show it to one of the lab staff and obtain a signature on your cover sheet. Lab 5: Memory

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Controller is
    Port ( SyncDataIn : in STD_LOGIC;
          clk : in STD_LOGIC;
          LOAD : out STD_LOGIC;
          SHIFT : out STD_LOGIC;
          CLEAR : out STD_LOGIC;
          DataReady : out STD_LOGIC);
end Controller;

architecture Behavioral of Controller is

   -- Constant definitions
   constant clk_freq   :integer := 10000000; -- 10 MHz clock
   constant baud_rate :integer := 115200; -- 115,200 baud
--   constant baud_rate :integer := 19200; -- 115,200 baud
   constant N_count    : integer := clk_freq/baud_rate;
   constant N_count_by2: integer := N_count/2;

   type state_type is (WaitForStartBit, WaitforNby2, ShiftBits, LoadOutputReg, AssertRxDone);
   signal curr_state, next_state : state_type;
   
   -- Counter signals
   signal count_N   : std_logic_vector(15 downto 0);
   signal count_bit : std_logic_vector(3 downto 0);
   -- Signals from Fsm to counter
   signal Bitcount_pulse : std_logic;
   signal reset_Nby2counter, resetAllCounters : std_logic;
   -- Signals from counter to FSM
   signal Nby2CountRchd, NCountRchd, BitCountRchd : std_logic;
   -- Other outputs from FSM
   signal shift_fsmo, load_fsmo, clear_fsmo, dataReady_fsmo : std_logic;
   
begin

counter_N_Nby2 : process (clk)
begin
   if rising_edge(clk) then
      if (resetAllCounters = '1') then
         count_N <= (others => '0');
         NCountRchd <= '0';
         Nby2CountRchd...

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