`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
module FSM_GREY_CODE(clk,rst,data_in_A,data_in_B,count_out);
input rst,clk;
input data_in_A,data_in_B;
output reg count_out;

reg [2:0] p_state,n_state;
parameter S0 = 3'b000,
         S1 = 3'b001, // GRAY sequence
         S2 = 3'b011,
         S3 = 3'b010,
         S4 = 3'b110;

always@(posedge clk,posedge rst)
begin
      if (rst == 1'b1)
      p_state <= S0;
      else
      p_state <= n_state;
end
////////////// code for FSM////////
always @(p_state,data_in_A,data_in_B)
begin
case (p_state)
S0: begin
if (data_in_A == data_in_B)
n_state <= S1;
else
n_state <= S0;
end
S1:
begin
if (data_in_A == data_in_B)
n_state <= S2;
else
n_state <= S0;
end
S2:
begin
if (data_in_A == data_in_B)
n_state <= S3;
else
n_state <= S0;
end

Part I: Prelab The block diagram of the receiver is shown below. A...