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Learning objectives 1. How to combine a controller (state machine) with a datapath (in this case, a counter) 2. Continue to develop skill with modular design, construction, and testing. 3. Continue to develop skill with the oscilloscope. Introduction The classic mechanical stopwatch is controlled by a single button: press to start, press again to stop, press a third time to reset. (Other versions have a separate clear button.) Your task in this lab is to construct an electronic stopwatch with a four-digit display (00.00-99.99 seconds) controlled by a single pushbutton switch. This system is an example of a combined datapath (in this case, the four-digit counter) and controller (the state machine that bridges between the pushbutton and the inputs to the counter). The system is diagrammed below: (tens) 0-9 counter 0-9 counter 7 segments (cathodes) CLEAR MUX'd display BUTTON DEBOUNCE / Controller driver SYNCH 4 digits (anodes) ENABLE 0-9 counter CLOCK 0-9 counter DIVIDER (hundredths) BEFORE COMING TO LAB Reading Low Carb VHDL Tutorial, Chapter 11 (Structural Modeling) Part I: Prelab 1. As part of Homework 3, you designed and simulated the following entities: A single digit (0-9) counter, with inputs En_in and Clear and outputs Q (4-bit count) and En_out. A state machine with a single (pushbutton) input and two outputs (to Enable and Clear the counter). In this lab you will need the counter and state machine. We will give you a VHDL model for a multiplexed seven-segment display. We will also provide you with a debouncer/synchronizer for the pushbutton input. 2. Download Lab4 lab files: a project (.xise) file, a top level file (lab4_shell.vhd) and the display and debouncer modules and the UCF file. Add your counter and state machine models to the project. 3. Using structural VHDL methods, instantiate two copies of your single digit counter and wire them together and to the multiplexed seven segment display. Tie the En_in input of the least significant digit's counter to '1'. Make a testbench for this counter and verify its operation by simulation. The goal of this step is to make sure that your single digit counter works properly. 4. Design a clock divider that takes a 10 MHz clock and divides it down to produce 100 ns pulses at a frequency of 1 MHz (i.e., the pulses are 1 s apart). Connect this signal to the En_in input of the least significant digit (instead of '1') and verify by simulation that the counter updates every microsecond. Make copies of your VHDL sources and simulation waveforms to include with your report. Show your simulations to one of the lab staff and obtain a signature on your cover sheet. IN THE LAB Part II: Modular build and test Follow these steps in the lab to assemble and test your stopwatch. To avoid problems, your project hierarchy should only contain the files you are currently using Read these steps through carefully so that, before starting, you can visualize in advance the flow of the design-simulate-build-test process and what each step is intended to accomplish. 1. Two-digit counter First you will build a two-digit BCD counter with external RUN and CLEAR controls. (a) Change the clock divider (part 4, above) so that the pulse frequency is 100 Hz rather than 1 MHz. (b) Modify the entity of the shell to have additional input ports for RUN and CLEAR, and an additional output port for the 100 Hz slow enable. (c) Use structural VHDL methods to wire the counter to the RUN and CLEAR ports. (d) In the UCF, connect RUN and CLEAR to slide switches and the slow enable to one of the "Pmod" accessory jacks on the Nexys 3 board. (e) Implement the design, configure the FPGA, and test it. The two digits should properly count (the less significant digit will change too fast to follow, but the more significant digit should be viewable). The RUN and CLEAR switches should properly control the counters. The slow enable signal, viewed with an oscilloscope, should be 100 Hz (if it isn't, your watch won't keep accurate time). Demonstrate to one of the lab staff and obtain a signature on your cover sheet. 2. Four-digit counter The previous step verified the basic connections in the system. Next, instantiate two more copies of the one digit counter and wire them in to make a full four digit counter. Implement this design on the FPGA and test it. Again verify that RUN and CLEAR work properly. You should also observe that the ones digit of the display changes every second. Demonstrate to one of the lab staff and obtain a signature on your cover sheet. 3. Four digit counter with one-button control Now you will add the state machine controller to your design, replacing the separate RUN and CLEAR switches with a single pushbutton control. (a) Remove the RUN and CLEAR input ports from the top level entity, and also remove the 100 Hz output port. In the UCF, comment out the lines for these three ports. (b) Add your state machine to the system by adding its VHDL file to the project and instantiating it as another component in the shell. Wire it to the counter, the 100 Hz clock divider, and the top level BUTTON port. (c) Change the clock divider from 100 Hz back to 1 MHz and simulate the system to make sure that the BUTTON input properly controls the counter via the state machine. Make a copy of the simulation waveform to include with your report. (d) Change the clock divider back to 100 Hz. Wire the BUTTON port through the debouncer to the state machine. Make sure that the BUTTON port is wired to a pushbutton in the UCF. (e) Implement this design on the FPGA and test it. If all goes well, the system should behave like a stopwatch!

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-- Additional Comments:
-- In the future, might try a different design following the Maxim MAX6816,
-- uses a counter instead of a shift register.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;

entity debouncer is
port( clk, switch : in STD_LOGIC;
dbswitch : out std_logic );
end debouncer;

architecture behavioral of debouncer is
constant REG_LEN : integer := 10; -- typ 10ms, lengthen for more delay
signal dbreg : std_logic_vector(REG_LEN-1 downto 0) := (others => '0');

begin

debounce:
process(clk, dbreg)
begin
if rising_edge(clk) then
if switch...
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