An arbiter is a circuit that allows at moest one subsystem at a time to use a shared resource. A four-way arbiter
is shown in the figure below. Each subsystem sets its request signal (i.e., req0, req1, req2, req3) to 1 when it
wants to use the resource. When the arbiter sets the grant signal (i.e., gnt0, gnt1, gnt2, gnt3) to 1, then the
subsystem uses the resource. When the subsystem finishes with the resource, it then sets its request back to 0.
While a subsystem is granted use of the resource, the other requests must wait; the active subsystem is not
Create a synthesizable VHDL model that implements this arbiter. There are twooperational modes:
priority and (2) round-robin. For the priority mode (designated by mode = 0), subsystem 0 has the
highest priority, with descending priority to subsystem 3 which has the lowest priority. A pending request
from a higher-priority subsystem takes precedence over a pending request from a lower-priority subsystem.
For the round-robin mode (designated by mode = 1), subsystems are granted requests in order, starting
with 0, then 1, 2, 3, and back to 0. A subsystem is skipped if it has no pending request.
All inputs and outputs in the design are synchronous. The arbiter operates on a 50 MHz clock signal
(clk). The arbiter can be reset (i.e., reset = 1) if necessary. Use the port names exactly as given in this
problem description. You are expected to erify/debug your model.
entity arbiter is
port ( rego, req1, req2, req3, mode, reset, clk: in std_logic;
gnt0, gnti, gnt2, gnt3: out std_logic
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clk_p: process(reset,clk) is
if(reset = '1') then
state <= idle;
state <= next_state;
end process clk_p;
gnt0 <= '0';
gnt1 <= '0';
gnt2 <= '0';
gnt3 <= '0';
next_state <= idle;
if(mode = '1') then
case state is
when idle =>
if(req0 = '1') then
next_state <= grant0;
elsif (req1 = '1') then
next_state <= grant1;
elsif (req2 = '1') then
next_state <= grant2;
elsif (req3 = '1') then
next_state <= grant3;
when grant0 =>...