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(c) Draw schematic of the hardware described by Verilog code. If flip-flops are used, indicate if they are level triggered or edge triggered (4 points) module mod_ a (x, y, a, b. c); input a, b, c; output X, y; wire [7:0] b. c; reg [8:0] x,y; always @ (a or b or c) begin if (a) begin X = b+ c; y =b-c; end else begin X = b -c; end end endmodule (Question 1) (10 points) (a) Consider the follow piece of code to implement a synchronizer (as shown in figure below). Does the code implement the required functionality? (Explain). If the code does not properly implement a synchronizer, modify the code as necessary. (3 points) in q1 q2 D Q D Q CLK input in; reg q1, q2; always @ (posedge CLK) begin ql = in; q2=q1; end (b) The following Verilog code should synthesize to a purely combinational logic function (3:1 multiplexor, where we don't care about the case when sel = 11). Does it? If not, fix the code so that there are no memory elements. (3 points) module mux_3tol ( (a,b,c, sel, out); input [1:0] sel; input a,b, c; output out; reg out; always @ (a or b or c or sel) begin case (sel) 2'b00: out=a; 2'b01: out==b; 2'b10: out=c; endcase end endmodule (Question 2) (10 points) (a) Design a module following schematic shows Verilog the for a rising-edge clock in drives the state transition appropriate inputs and triggered synchronous FSM (the "STATE=000" at the next rising below. edge If of input clock. "RESET" (5 points) outputs). = 1, The the value FSM of will input switch "MOVE" to MOVE 3 RESET Fido STATE CLK 000 1 001 1 100 111 1 1 1 1 . 011 010 101 1 110 1 // synchronous reset module Fido (CLK, RESET, MOVE, STATE); input CLK, RESET, MOVE; output reg [2:0] STATE; always @ ( ) begin if ( ) STATE <= ; else case (STATE) 3'b000: STATE <= 3'b001: STATE <= 3'b010: STATE <= ; 3'b011: STATE <= ; 3'b100: STATE <= ; 3'b101: STATE <= ; 3'b110: STATE <= 3'b111: STATE <= ; endcase end endmodule design, (b) Now you are required to rewrite your Verilog code in section to describe a FSM synchronous. (5 points) where the "RESET" input is an asynchronous reset prior and "STATE" transition is // asynchronous reset module Fido (CLK, RESET, MOVE, STATE); input CLK, RESET, MOVE; output reg [2:0] STATE; always @ ( ) begin if ( ) STATE <= ; else case (STATE) 3'b000: STATE <= ; 3'b001: STATE <= ; 3'b010: STATE <= ; 3'b011: STATE <= ; 3'b100: STATE <= ; 3'b101: STATE <= ; 3'b110: STATE <= ; 3'b111: STATE <= ; endcase end endmodule

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