1. A an external memory unit (shown in the block diagram below) can hold 8192 8-bit words. [Note: This is, then, an 8kbyte memory unit.] The unit is controlled by a controller unit via input “R/W’”. Note that this notation implies that a 1=Read and a 0=Write. Further, the memory unit is enabled only when input “E’” is 0. The signals in the address pins determine with memory location is selected, or addressed. So, for example, if A12-A0 = 11100001100102 = 1C3216 = 721810, then we are pointing to memory location 7218 (out of 8192) in the memory chip. Describe the steps that one would have to follow to store the word “110001012” (i.e. C516) from the controller to the memory chip. Be very specific about the values signals T7-T0, M15-M0, EN, and READ should take and in which order they could be written.

Note: The first three steps can occur in interchangeable order (or concurrently), but the chip should be enabled only once all three previous steps are completed.

2. the same controller unit in problem 1, but now we have access to three 8kbyte memory units, Unit0, Unit1, and Unit2, as shown in the block diagram below. Only one of the three memory units should be enabled at any point in time. Each memory unit should address only a certain range of memory locations from the controller. The exact set of memory locations is:
• Unit0 is related to the controller’s memory locations 000016 - 1FFF16.
• Unit1 is related to the controller’s memory locations 200016 - 3FFF16.
• Unit2 is related to the controller’s memory locations E00016 - FFFF16.

Design the logic circuit to correctly enable each memory unit. Note that logic 0 is required to enable each one of the memory units.
Hint: Spend some time to identify the following:
• How many inputs, say N, does your circuit need?
• Which signals from your controller should be connected to these N inputs?

Extra: What are signals A12-A0 connected to?

3. Write the VHDL statements to implement problem 1.

4. Write a full VHDL program to implement the circuit you designed in problem 2. In the architecture, you must use if statements.

5. Write the architecture of the 32-bit 2-to-1 MUX from homework one, using case statements.

6. Write the architecture of the 32-bit 2-to-1 MUX from homework one, using selected signal assignment statements.

7. Write a VHDL module that .finds the average value of four 16-bit unsigned numbers that are represented by std_logic_vectors in the input. Note that division by four is best accomplished by shifting. Round off your 16-bit answer to the nearest integer.

8. Consider the following VHDL statements:
T1 <= not A and not B and I0;
T2 <= not A and B and I1;
T3 <= A and not B and I2;
T4 <= A and B and I3;
F <= T1 or T2 or T3 or T4;

Recalling that the not operator has precedence over the and and or operators, do the following:
i. Draw a MUX that implements function F.
ii. Write a selected signal assignment statement that describes the MUX.

1. A an external memory unit (shown in the block diagram below) can...