Project Description

Your task is to implement a 16-bit version of the ALU using Verilog HDL and analyze by simulating it in ICARUS Verilog on timberlake. The ALU operations that should be included are ADD, SUB, AND, OR, and SLT. A Zero output is not required. For simplicity, overflow does NOT need to be implemented. A functional (zero delay) simulation should be used to verify the circuits works properly and a unit gate delay model simulation should be used to evaluate performance. Structural (not behavioral) Verilog must be used.

Simulation & Writeup
A written report should be submitted which includes circuit diagrams of the ALU (down to the gate level), functional (zero delay) simulation results proving that the ALU works properly, and unit gate delay simulation results which will be used to analyze performance and gain a better understanding the effect of delay on digital design. The following checklist will help ensure that you have included all the required components with your writeup.
• Circuit diagrams of the ALU down to the gate level.
• Critical path & delay of the ALU under the unit gate delay model.
• Gate cost of the ALU.
• Functional (zero delay) simulation results for the ALU proving the Verilog implementation of your circuits work properly. Multiple data sets should be used to prove this. There should be four data sets for each operation (ADD, SUB, SLT, AND, OR).
• Analysis (including specific examples) of the temporal dependence of the delay on the previous set of inputs applied to the ALU under the unit gate delay model. At least 5 specific example should be simulated to show this. The specific examples must be highlighted in your writeup. They need not all be the same operation. For example, one may be for ADD, one for AND, and three for SLT.
• Analysis of the average delay across 1,000 randomly selected input patterns for each the ALU using the unit gate delay model. Specifically state how this average compares to the critical path delay. You should not include a list of the detailed simulation results for this portion, but rather a summary indicating the average delay across all 100 samples for the ALU. Setting up 1,000 simulation sets manually and manually analyzing the results is not an efficient way to do this. Utilize your coding skills to make this task easier.

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//// 16-bit version of ALU Design
//// Language : Verilog.
//// Simulation: ICARUS verilog

////////////////////// Main Module /////////////////////

`timescale 1ns / 1ps

module ALU(Y,C,N,A, B, Op);
   output [15:0] Y; // Result.
   output C; // Carry.
   output N; // Negative.
input [15:0] A; // Operand.
   input [15:0] B; // Operand.
   input [2:0] Op; // Operation.

   wire [15:0] AS, And, Or;
   wire Cas,slt1,s;
   // The operations
carry_select_adder_subtractor addsub(AS, Cas, A, B, Op[0]);      
// Op == 3'b000, 3'b001
   andop aluand(And, A, B);                                             
// Op == 3'b010
   orop aluor(Or, A, B);
// Op == 3'b011
SLT slt2(slt1, A,B);
// Op == 3'b100
nor #1 (s, Op[1], Op[2]);   // s == 0 => a logical operation, otherwise and arithmetic operation.
   and #1(C, Cas, s);
and #1(N, Y[15], s); // Most significant bit is the sign bit in 2's complement.

multiplexer_8_1 muxy(Y, AS, AS, And, Or, {15'b0,slt1}, 16'b0, 16'b0, 16'b0, Op); // Select the result.
endmodule // alu

module andop(Y, A, B);
   output [15:0] Y; // Result.
   input [15:0] A; // Operand.
   input [15:0] B; // Operand.

   and #1(Y[0], A[0], B[0]);
   and #1(Y[1], A[1], B[1]);
   and #1(Y[2], A[2], B[2]);
   and #1(Y[3], A[3], B[3]);
   and #1(Y[4], A[4], B[4]);
   and #1(Y[5], A[5], B[5]);
   and #1(Y[6], A[6], B[6]);
   and #1(Y[7], A[7], B[7]);
   and #1(Y[8], A[8], B[8]);
   and #1(Y[9], A[9], B[9]);
   and #1(Y[10], A[10], B[10]);
   and #1(Y[11], A[11], B[11]);
   and #1(Y[12], A[12], B[12]);
   and #1(Y[13], A[13], B[13]);
   and #1(Y[14], A[14], B[14]);
   and #1(Y[15], A[15], B[15]);
endmodule // andop

module orop(Y, A, B);
   output [15:0] Y; // Result.
   input [15:0] A; // Operand.
   input [15:0] B; // Operand....

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