`timescale 100ps/1ps

module bfloat16_add(
in_A,
in_B,
select,

out_result

);

input [15:0]    in_A;
input [15:0]    in_B;
input             select;

output[15:0]    out_result;
/* Write your own code below*/

reg [15:0] in_B_cal;
reg [7:0] man_A_pre;
reg [7:0] man_B_pre;
reg [7:0] man_A;
reg [7:0] man_B;
reg [8:0] mantissa;
reg [8:0] mantissa_norm;

reg [15:0] result;
reg [7:0] exponent;
reg [8:0] exponent_norm;

reg [3:0] shift;

reg sign;
reg is_sign_diff;
reg is_A_bigger;
reg [7:0] exponent_diff;

assign out_result = result;

always @ *
begin
if (select)
   in_B_cal[15] = ~in_B[15];
else
   in_B_cal[15] = in_B[15];

in_B_cal[14:0] = in_B[14:0];

if (in_A[14:0] == 15'd0)          //A=0
   result[15:0] = in_B_cal[15:0];

else if (in_B_cal[14:0] == 15'd0)    //B=0
   result[15:0] = in_A[15:0];

else if (in_A[14:0] == 15'b111111110000000 | in_B_cal[14:0] == 15'b111111110000000) //infinity
   result[15:0] = 16'b0111111110000000;

else if (in_A[14:7] == 8'b11111111 | in_B_cal[14:7] == 8'b11111111) //NaN
   result[15:0] = 16'b0111111110000001;

else if ( (in_A[14:0] == in_B_cal[14:0]) & (in_A[15] != in_B_cal[15]) ) //A+B = 0
   result[15:0] = 16'd0;

//Normal case
else
begin
   if (in_A[14:7] > in_B_cal[14:7]) //e_A > e_B
   begin
         is_A_bigger = 1;
         exponent_diff = in_A[14:7] - in_B_cal[14:7];
   end

   else if (in_A[14:7] < in_B_cal[14:7]) //e_A < e_B
   begin
         is_A_bigger = 0;
         exponent_diff = in_B_cal[14:7] - in_A[14:7];
   end

Digital Logic Design Q1) It is required to design a simple control...