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Organization of Digital Computer Lab LAB 2 In this lab, we want you to complete a Single Cycle MIPS Processor. Please see the associated files with this manual. 1 Single Cycle Processor Figure 1 shows a single cycle processor. Figure 1 : Datapath. 1 The instruction execution starts by using the program counter to supply the instruction address to the instruction memory. After the instruction is fetched, the register operands used by an instruction are specified by fields of that instruction. Once the register operands have been fetched, they can be operated on to compute a memory address (for a load or store), to compute an arithmetic result (for an integer arithmetic-logical instruction), or an equality check (for a branch). If the instruction is an arithmetic-logical instruction, the result from the ALU must be written to a register. If the operation is a load or store, the ALU result is used as an address to either store a value from the registers or load a value from memory into the registers. The result from the ALU or memory is written back into the register file. Branches require the use of the ALU output to determine the next instruction address, which comes either from the ALU (where the PC and branch oset are summed) or from an adder that increments the current PC by four. The thick lines interconnecting the functional units represent buses, which consist of multiple signals. The arrows are used to guide the reader in knowing how information ows. Since signal lines may cross, we explicitly show when crossing lines are connected by the presence of a dot where the lines cross. Create a new project in Vivado using the files listed below. Find these files under lab2 on the Canvas. mips 32.v, datapath.v, control.v, ALUControl.v, instruction mem.v, mux2.v, register file.v, sign extend.v, ALU.v, data memory.v, and tb mips 32. Now you have a mips processor which is able to run these 7 instructions: We want you to complete this processor and add a new set of instructions to it. 2 Note:: For the ease of implementation we made some changes in the original MIPS architecture. Instead of 32 bits our Program Counter (PC) has 10 bits. This will lead to a smaller Instruction memory. 2 MIPS Instructions MIPS has 3 different instruction types. Table 1 shows these three instruction formats. In our simple implementation of MIPS we only have some R-type instructions plus load word and store word and addi instructions which are I-type. Table 1 : Instruction Set. 2.1 R-Format Below you see the R-Format instruction fields. Here is the meaning of each name of the felds in MIPS instructions: • op: Basic operation of the instruction, traditionally called the opcode. • rs: The first register source operand. • rt: The second register source operand. 3 • rd: The register destination operand. It gets the result of the operation. • shamt: Shift amount. • funct: Function. This field, often called the function code, selects the specific variant of the operation in the op field Here is an example for add instruction: N ¯ OTE: Our shift instructions is another major difference with the original MIPS. Shift is RFormat Instruction but here we set the opcode to be 48(110000). for shift instructions we want to shift rs register shamt times and store back the result in the rd register. We are not using the rt register field for shift instructions. For example, here we want to shift register R3 2 times to left and store back the result in the register R1. Shift instructions here are a little bit different from the MIPS architecture: • The opcode for shift instructions is 48(110000). • The second operand in the shift instructions is the shamt comes from the sign extends unit. The sign extends unit output is 32 bit (imm value) but we only want to use 5 bits of it. So for the shift amount in the alu use b[10:6]. • The rt field in the shift instructions is always zero. (please look at the sll example) • Sra is shift right arithmetic. It means that we want to insert the sign bit. you can use the arithmetic shift operator but keep in mind that for this operator the first operand should be a signed value. 2.2 I-Format Below you see the I-Format instruction fields. They are same as R-Format except they have an address (or immediate value) field. Branch is also a I-Format. In the beq instruction we want to compare two registers and if they are equal update the pc. Here is an example for beq instruction. If register one and register three are equal we want to branch to 2 instructions after the current instruction: 4 N ¯ OTE: The address in the branch instruction is a relative address. It means that we are adding the current PC with the address field in the beq to find the new PC. The address field is bit 0 to 15 in the instruction which goes to the Sign-extend module. Sign extend gives us a 32-bit result. We need to shift this result to the left 2 times (reason : here Memory is byte addressable). Pay attention that PC is only 10 bits. So we only need the lower 10 bits of the shift result here to add to the current PC. 2.3 J-Format Below you see the J-Format instruction fields. Here is an example for jump instruction. We want to jump to address 2: N ¯ OTE: The address in the Jump instruction is an absolute address. It means that the new PC will be the value we have in the address field of jump instruction. N ¯ OTE: Pay attention that PC is only 10 bits. So we only need the lower 10 bits of the address here. 3 MIPS processor After you modify the code your processor would be something like this. 5 use this table to modify control, ALUControl, and ALU files. 4 Test New Instructions To test each new instruction you need to find the binary code of that instruction and add it to the instruction memory. Chapter 2 of the book will help you to write your own instructions. 6 4.1 Addressing Pay attention that memories in MIPS are byte addressable. It is the reason that we increase program counter (pc) by 4. Also if you look at the instruction memory and data memory code you will see that we are not using the lower 2 bits of the address. This means the address is byte address and since we want to access words we can omit the lower 2 bits. 5 Assignment Deliverables Your submission should include the following: • Block designs. (mips 32.v, datapath.v, control.v, ALUControl.v, instruction mem.v, mux.v, register file.v, sign extend.v, ALU.v, data memory.v) • A report in pdf format. Follow the rules in the ”sample report” under ”additional resources” in the Canvas. Note1: Compress all files (11 files : 10 .v files + report) into zip and upload to the CANVAS before deadline. Note2: Use the code samples that are given. The module names and the port names should exactly look like the code sample otherwise you lose points. Note3:Please make sure that the module definitions in your project (input and output signals) are the same as what you see here. Code 1: mips 32. module mips_32 ( input clk , reset , output [31:0] result ); Code 2: datapath. module datapath ( input clk , reset , input reg_dst , reg_write , input alu_src , input mem_read , mem_write , input mem_to_reg , input [3:0] ALU_Control , input branch , jump , output [31:0] datapath_result , output [5:0] inst_31_26 , output [5:0] inst_5_0 ); 7 Code 3: control. module control ( input reset , input [5:0] opcode , output reg reg_dst , mem_to_reg , output reg [1:0] alu_op , output reg mem_read , mem_write , alu_src , reg_write , branch , jump ); Code 4: ALUControl. module ALUControl ( input [1:0] ALUOp , input [5:0] Function , output reg [3:0] ALU_Control ); Code 5: mux. module mux #( parameter mux_width = 32) ( input [ mux_width -1:0] a,b, input sel , output [ mux_width -1:0] y ); Code 6: instruction mem. module instruction_mem ( input [9:0] read_addr , output [31:0] data ); Code 7: register file. module register_file ( input clk , reset , input reg_write_en , input [4:0] reg_write_dest , input [31:0] reg_write_data , input [4:0] reg_read_addr_1 , input [4:0] reg_read_addr_2 , output [31:0] reg_read_data_1 , output [31:0] reg_read_data_2 ); Code 8: sign extend. module sign_extend ( input [15:0] sign_ex_in , output reg [31:0] sign_ex_out ); Code 9: ALU. module ALU ( input [31:0] a, input [31:0] b, input [3:0] alu_control , output zero , output reg [31:0] alu_result ); 8 Code 10: data memory. module data_memory ( input clk , input [31:0] mem_access_addr , input [31:0] mem_write_data , input mem_write_en , input mem_read_en , output [31:0] mem_read_data ); reg [31:0] ram [255:0]; Note4:: we are going to test the content of data memory so please especially don’t change the highlighted lines above.

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`timescale 1ns / 1ps
// Company:
// Engineer:
// Create Date:
// Design Name:
// Module Name: datapath
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
// Dependencies:
// Revision:
// Revision 0.01 - File Created
// Additional Comments:

module datapath(
    input clk, reset,
    input reg_dst, reg_write,
    input alu_src,
    input mem_read, mem_write,
    input mem_to_reg,
    input [3:0] ALU_Control,
    input branch, jump,
    output [31:0] datapath_result,
    output [5:0] inst_31_26,
    output [5:0] inst_5_0

    reg [9:0] pc;
    wire [9:0] pc_plus4;// = 6'b000000;
    wire [31:0] instr;
    wire [4:0] write_reg_addr;
    wire [31:0] write_back_data;
    wire [31:0] reg1, reg2;
    wire [31:0] imm_value;
    wire [31:0] alu_in2;
    wire zero;
    wire [31:0] alu_result;
    wire [31:0] mem_read_data;

always @(posedge clk or posedge reset)
          pc <= 10'b0000000000;
          pc <= pc_plus4;

assign pc_plus4 = pc + 10'b0000000100;
/*   instruction_mem inst_mem (

    assign inst_31_26 = instr[31:26];
    assign inst_5_0 = instr[5:0];

    mux #(.mux_width(5)) reg_mux
    (   .a(instr[20:16]),

    register_file reg_file (

    sign_extend sign_ex_inst (

    mux #(.mux_width(32)) alu_mux
    (   .a(reg2),

    ALU alu_inst (

    data_memory data_mem (

    mux #(.mux_width(32)) writeback_mux
    (   .a(alu_result),
    assign datapath_result = write_back_data;


    reg [9:0] pc;
    wire [9:0] jump_mux_out;// = 6'b000000;
    wire [31:0] instr;
    wire [4:0] write_reg_addr;
    wire [31:0] write_back_data;
    wire [31:0] reg1, reg2;
    wire [31:0] imm_value;
    wire [31:0] imm_value_shifted;
    wire [31:0] alu_in2;...

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