 # Verilog Assignment

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Homework 10 1) Write a 16 bit full adder module using generate (lecture 15 section 1 slide 3) • inputs are A and B, output is C • should have a carry out and detect overflow, both should be module outputs your answer should be a module written in System Verilog 2) write an integer multiply function using arithmetic shifts and adds only (see lecture 15 section 2 slide 24) • inputs are A and B, and output is C, assume 8 bits your answer should be a function written in System Verilog The code first initializes mul to zero then adds a A<<i for every nonzero value of B[i] then since it starts at i=1 it handles the non shifted value for odd numbers. If you tried larger numbers you may have noticed a problem due to the way the shift handles overflow Note that the proper result is 165 and it generates a 119!!! The solution to this is to use parenthesis around the shift 3) write an integer divide function without using a divide (/) (see lecture 15 section 2 slide 32) • inputs are A and B, and output is C, assume 8 bits, also pass back the remainder, there are several ways to do this shown in the lecture your answer should be a function written in System Verilog 4) Write an integer divide function using the pseudocode in Harris and Harris on page 254, pseudo code is a nonlanguage specific way to specify a procedural code Note that the code in the book isn’t very specific on some operations, Let me provide some clarification The line R={R’<<1,A[i]) must be implement as Rs = R<<1; Rs = {Rs[7:1],A[i]}; // You see only the high order bits of Rs are concatenated with A[i] Write a module containing this function that calculates the A/B and the remainder It will require problem solving skills to figure out how to do this with the tools you have available. Mainly from Harris and Harris and lecture 15. Using this code and a test you devise create waveforms that the your code for finding the integers A/B and the remainder for the cases where A=15 and B=5 and A=17 and B=5. your answer should be a function written in System Verilog and screen grabs of waveforms for these cases 5) Write an 8 bit ripple adder function using the 1 bit Full Adder function (Lecture 14 slide 14, homework 9 problem 9, and Exam 2 problem 2) your answer should be a function written in System Verilog 6) Write an integer ALU with these opcodes and functions. This should be done with the functions above and a case statement to handle each opcode. Note that this has some similarity to Lab2 but functions make it easier to implement in these case statements. • 0010 A+B=C implement with a full adder • 0100 A-B=C implement with two's compliment and a full adder • 1101 A*B=C implement using code developed above • 1110 A/B=C implement using code developed above(3 or 4 your choice) • 0110 A&B=C boolean expressions • 0101 A|B=C Boolean expressions Provide tests using \$display of input and output captured as an image for Opcode 0010 A=5, B=13 Opcode 0100 A=27 B=7 Opcode 1101 A=3 B=9 Opcode 1110 A=27 B=9 Opcode 0110 A=15 B =27 Opcode 0101 A=15 B=27 your answer should be a module containing necessary functions written in System Verilog, and images from testes for these cases. A good way to capture an label these waveforms is to drop them into a powerpoint file labled carefully and convert to pdf, Provide all code clearly labeled in code files. If the grader can’t figure how where the answers are for specific questions he will count that as zero points This will allow us to do subtraction Homework 11 For these exercises use System Verilog. I recommend you read through all the problems before beginning. 1) We have 8bit serial data. Using a bank of 1 bit shift registers and a module perhaps using a generate to create instances to make a FIFO buffer, or using an 8bit wide shift register such as ShiftRegWd Lecture 15 slide 20. Then use this to create module that does a 5 point moving average from file with coefficients in coef.csv. The input data is in .csv file xinput.csv. write output to file filterma.csv. Include the code and .csv file in the homework submission. Since you will have written to a .csv file open it in excel and make a plot of input versus index, and output versus index. To make this easier use this testbench and fill in the modules needed, see lecture 15 material. Submit all the code files including the testbench I gave you. 2) Now use this to make a Butterworth filter. The coefficients in the numerator, and the coefficients in the denominator are come from file coef2.csv. The input is xdata.csv and dump the input and output results to a file named filerarma.csv file. Include the code and output .csv file in the homework submission. Referring to Lecture 15 slide 25-37 where we have set f = 0.25. To help with this this is the testbench I used. Submit all your code files including the testbench I gave you. Pull your result into excel and choose data analysis and fourier transform. You may have to add data analysis to your excel addins (File, options, add-ins, manage excel addins (it is at the bottom) Go , click analysis toopack and hit OK). Include in your homework submission a plot the magnitude of the Fourier transform versus the frequency index of the input data and the Butterworth filtered data. Zoom into the first 128 points which will be up to Fnyquist. You are free to multiply the output by a constant to match the input data in the passband. 3) The objective of this next homework problem is to code an 8 bit LFSR random number generator like the one shown in the figure below. Write System Verilog code for an 8 bit LFSR. Note that this 8 bit LFSR combines bits 7,5,4,3 to create bit 0 in the feedback. Submit the code file. 4) Write a test bench for the LFSR code and load the seed 11111111, and generate the first 10 random numbers. Submit the test bench and a csv file generated by the test showing the first 10 random numbers generated, and an image of the waveform. 5) Port your LFSR code from problem 3 into Quartus and generate the RTL Netlist and capture the image in pdf form. Submit this image with your program solution, and answer this question: Are the blocks what you anticipated referring back to the figure in problem 3? If not, why not?

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