The purpose of this assignment is to gain a better understanding of the operation of computer arithmetic circuits by constructing working models using a publicly available logic simulator. We will explore circuits that perform basic arithmetic operations on integer and floating-point numbers.
The logic simulator I am asking you to use in carrying out this assignment is Logisim, written by Carl Burch. It can run on any computer with a Java Virtual Machine installed. The latest Windows version can be downloaded here. The program may be run directly without any complex installation or uninstallation process. I recommend that you first familiarize yourself with its operation by building some small combinational and sequential logic circuits before proceeding to the following assignment.
Assignment (Due Wednesday, March 4 by 5:00 p.m.):
Part A: Construct a circuit that will multiply two 8-bit signed binary integers in two's complement format, producing a 16-bit signed result. For this part of the assignment you may use any of the basic logic gates, multiplexers, flip-flops, registers, etc. available in Logisim or its standard libraries, but you may not use the multiplier from the Arithmetic library. Using a ROM from the Memory library is also not allowed. (Precomputing results and storing them in a lookup table for later access is a legitimate design technique in some situations, but it would bypass the main point of this assignment, which is to understand the inner workings of arithmetic circuits.) Your multiplier may use all combinational logic, or a mix of combinational and sequential logic. When you have a completed implementation, test it by providing several pairs of numbers as inputs. Make sure you thoroughly exercise the circuit by using all combinations of positive and negative operands, both large and small numbers as operands (including positive and negative boundary cases), one or both operands equal to zero, etc. (This way there will be no surprises when I test your submitted circuit on my own machine.)
Part B: Now construct a circuit that will multiply a pair of numbers in IEEE-754 single precision floatingpoint format. This time, it is OK to use the built-in integer multiplier function from Logisim's Arithmetic library to do the actual multiplication of the significands; but you will still need to figure out and build in the logic to un-bias, add, and re-bias exponents as needed, normalize the product and adjust the exponent, etc. to produce the final result in IEEE-754 format. As in Part A, once you have your floating-point multiplier circuit constructed, test it with a variety of positive and negative, small (much less than 1) and large numbers, and zero, as inputs. (To keep things more manageable, you do not have to make the circuit handle NaNs, denormalized numbers, or positive/negative infinity; it only has to work for normalized real numbers and positive/negative zero.)
This material may consist of step-by-step explanations on how to solve a problem or examples of proper writing, including the use of citations, references, bibliographies, and formatting. This material is made available for the sole purpose of studying and learning - misuse is strictly forbidden.
The entire circuit is driven by a free running clock, and requires 9 clock cycles for the entire calculation. Input A is the 8-bit multiplicand and Input B is the 8-bit multiplier. Multiplier (that is, Input B) is stored in an 8-bit parallel load shift-register. To load data into 8-bit Parallel load Shift register, Load signal has to be one. So, in the first clock cycle, Load input pin is set to 1, and this loads the value of multiplier (after converting to 2’s complement form) into the register. After that, the Load signal is reset to 0 to enable the multiplication to start.
The shift register is dependent on another input signal ShiftEnable, which when 1, allows the bits to be shifted. Now, in every subsequent clock cycle, 1 bit is shifted and multiplied (using 2-bit AND gates) with each of the 8 bits of multiplicand to compute the partial products. The result is added to the existing partial sum which is fed back in a loop from an 8-bit register. The LSB of this partial sum is shifted into an 8-bit shift register. And the rest of the 7 most significant bits along with carry-out of the adder are stored in the 8-bit register. So, exactly 8 clock cycles are needed to complete the multiplication. This iterative shifting and adding operation help us achieve the desired serial multiplication....
This is only a preview of the solution. Please use the purchase button to see the entire solution