Readings: Computer Systems (Fourth Edition), by J. Stanley Warford

It can be handwritten & scanned
- or -
You can download Visio from Dreamspark
- or -
You can use a circuit & or diagram software of your choice

Problem 1: Draw the Design Table, the K-maps and the circuit for:
a) Construct an SR flip-flop from a D flip-flop
b) Construct a T flip-flop from a JK flip-flop

Refer to Figs11.17 thru 11.19 & Worked Example for #7

The most common mistake is to confuse which flip-flop you are making and which one you are using. “from a _ flip-flop” is the flip-flop shown in your circuit. The final circuit should have a design table that matches the flip-flop that you are constructing.
Problem 2: First, draw the logic diagram, then an analysis table (Excel works nicely for this because you can hide the columns that you are not working on at the moment) and then finally, draw the state transition diagram for a sequential circuit with two JK flip-flops, FFA and FFB; two inputs X1 & X2, with flip-flop inputs:
JA = X2 KA = X1 B’
JB = X1 X2 A KB = X1’ + X2’
And output:

Z = X1 A’ + X2 B’

Refer to Figs 11.27 thru 11.32 – The Truth Table should look like 11.28

I do not care for the table in 11.29, however it may help you create the diagram Also see Chapter 11 – additional worked Example for #11
Problem 3: Textbook page 593, #16 (d) Show the Truth Table, the K-maps (There will be two – one for each Flip-Flop) and then finally draw the circuit.
Refer to Figs 11.32 thru 11.35 (Though I prefer the circuit drawn as one diagram) Also see Chapter 11 – additional worked Examples
Problem 4: A sequential circuit has three state registers (or flip-flops) and 3 inputs

(a) How many states does it have?
(b) How many transitions from each state does it have?
(c) How many total transitions does it have? Read Section 11.2
Problem 5: Textbook page 594, #21(a)

Study Fig 11.48 and read the explanation below it carefully.

Hint: the PROM will have 6 address lines going directly into the chip and four going to the chip select, the RAM will have 5 address lines going directly into the chip and 5 going to the chip select, and the 4-port I/O will have two address lines going directly into the chip and 8 going to the chip select. Note the book’s hint that the addresses are in decimal.
(a) Draw the Full Address decoding – Similar to Fig 11.48
(b) Include a table similar to Fig 11.47
(c) Draw a Memory Map like in Fig 11.50 and show which addresses each chip is enabled
(d) Can you add additional chips on this bus? Explain

Readings: Computer Systems (Fourth Edition), by J. Stanley Warford...