Question 2 (12 marks)
Consider the following circuit, with output terminals a and b.
(a) [8 marks] Find the Th ́evenin equivalent circuit.
(b) [4 marks] Now assume a 20 Ω load resistor is attached across the output terminals of the circuit. Find the power of the 2 A current source. It is generating or consuming power?
Question 3 (16 marks)
In the circuit below, a sinusoidal voltage source VS(t) = Vm cos(ωt) V is applied to a load consisting of an inductance L, resistance R and capacitance C, connected in series. VR(t) is the resistor voltage.
PSfrag replacements VS
(a) [2 marks] Obtain an expression for the total impedance Z in terms of R, L, C and ω.
(b) [2 marks] Use your answer to part (a) to obtain an expression for the transfer function HR(ω) that is defined to be the ratio of the resistor voltage phasor VR to the source
voltage phasor VS:
(c) [4 marks] Find the value of ω that will ensure the source voltage and resistor voltage are in phase.
(d) [2 marks] Assume the magnitude of the source voltage is Vm = 5 V . For your value of ω in part (c), what is VR(t)?
(e) [4 marks] Find a value of ω that will ensure the source voltage and resistor voltage have ◦
In the following questions, assume that L = 2 H, R = 18 Ω and C = 50 mF.
a phase difference of 45 .
(f) [2 marks] For your value of ω in part (e), explain whether the resistor voltage leads or lags the source voltage.
Question 4 (12 marks)
In the following dc circuit, the switch has been open for a long time. The switch is closed at t = 0 s.
+ 24 V
(a) [2 marks] Determine the current i (0−) immediately before the switch is closed. 1
(b) [2 marks] Determine the capacitor voltage v (0−) immediately before the switch is closed. 1
(c) [2 marks] Determine the current i1(0+) immediately after the switch is closed.
(d) [2 marks] Determine the capacitor voltage v1(0+) immediately after the switch is closed.
(e) [2 marks] Determine i1(∞), the steady state value for i1 after the switch has been closed for a long time.
(f) [2 marks] Determine v1(∞), the steady state value the capacitor voltage after the switch has been closed for a long time.
Explain and justify your answers by drawing appropriate circuit diagrams and by referring to known dc transient and steady-state behaviour of capacitors and inductors.
Question 5 (14 marks)
In the following circuit a sinusoidal source voltage V has rms amplitude Vrms, phase angle θv = 0◦, and angular frequency ω. The load consists of a resistor R and capacitor C connected in series. It consumes real power P with leading power factor PF%.
Assume initially that the inductor is not connected to the circuit. (a) [6 marks] Write down nested formulae for the following:
(i) The power angle θ, in degrees; (ii) The rms current Irms;
(iii) The reactive power Q of the load;
(iv) R and X, the real and complex components of the load impedance Z = R + jX;
(v) The capacitor C;
(vi) The phasor current I.
Note: By nested formulae we mean that the variables used in each formula can only include any variables that have been previously defined. Thus θ may be defined in terms of Vrms, P, ω, and PF, while Irms may be defined in terms of Vrms, P, ω, PF and θ, etc.
NowassumeVrms =1000V rms,ω=1000rad/s,P =4000W andPF =50%.
(b) [3 marks] If the inductor is added to the load in parallel as shown, find the inductor
value that will yield a load power factor of 100%.
(c) [5 marks] Find the range of inductor values that will yield a load power factor of 90 % or better. State which inductor values will yield an inductive load and which will give a capacitive load.
Question 6 (12 marks)
A balanced Wye-Delta three-phase power circuit has line-to-neutral source voltages of 220 V rms. The source angular frequency is 1000 rad/s, and the source voltages follow a positive phase sequence. The load impedances each consist of a 30 Ω resistor in series with a 5 mH inductor. The line impedances can be modeled as a 1 Ω resistor in series with a 0.5 mH inductor.
(a) [4 marks] Find the line current phasor IbB and load current phasor IBC. Support your calculations with an appropriate circuit diagram.
(b) [3 marks] Find the real and reactive power of the Wye source.
(c) [3 marks] Find the total real and reactive power of the line impedances, and the real
and reactive power consumed by the Delta load.
(d) [2 marks] Confirm that your answers in parts (b) and (c) are consistent with the con- servation of energy.
Question 7 (8 marks)
A digital logic system has three inputs I1, I2, and S as well as two outputs O1 and O2. When S is low, we have O1 = I1 and O2 = I2. When S is high, we have O1 = I2 and O2 = I1.
(a) [2 marks] Write down the truth tables for the output logic functions O1 and O2.
(b) [2 marks] Use laws of Boolean algebra to find the minimum sums-of-products (SOP)
expressions for O2.
(c) [2 marks] Show how to implement your minimum SOP form for O2 using logic gates.
You may use at most 4 logic gates.
(d) [2 marks] Show how to implement logic function O2 using a 3-to-8 decoder and one other logic gate.
Question 8 (6 marks)
(a) [2 marks] Is the following logic equation valid? Justify your answer.
AB = (A + B)(A + AB)
(b) [4 marks] In the circuit shown below, the switches are controlled by logic variables as
(1) If A is high, switch A is closed, and if A is low, switch A is open.
(2) If B is high, the switch labeled B is open, and if B is low, the switch labeled B is closed.
(3) Switches C and D behaves the same as switch B.
(4) The output variable E is high if the output voltage is 5 V, and is low if the output
voltage is zero.
Obtain a logic expression for E. Briefly explain your answer (write about 20 to 30 words).
Question 9 (10 marks)
The diode in the following circuit has a simple piecewise linear current-voltage relationship with a threshold value vf = 0.6 V . The dc battery has a fixed voltage of 3.4 V . The variable resistor RL can take values in the range [0, 100 Ω]. The constant input voltage is 8 V .
PSfrag replacements 8V
+ 3.4 V
(a) [4 marks] What is the smallest value of RL for which the diode is on? Justify your answer.
(b) [6 marks] Let iD be the current through the diode. Express iD in terms of RL and hence plot the graph of iD against RL, for RL in the range [0,100 Ω].
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