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*** Assume all flip flops, counters and registers are active high data inputs, active low Reset pins, level triggered and that output bit A is always the leat significant bit Name _________________________________ 1.) Consider a simple series connected , 4 stage J K Flip Flop ripple up counter circuit : ( see Fig 10-2 in Schaums ) a) If the clock input signal is a 16 kHz square wave; then what will the output frequencies be at outputs Q1, Q2, Q3 and Q4 ? F1=__________ F2 = _________ F3 = _____________ F4= ____________ b) If a 5th and 6th flip flop stage are cascaded to this counter, what will the frequencies be at Q5 and Q6 ? F5 = _____________ F6 = _________________ c) If the output of a nand gate were connected to all of the active low reset pins on each FF in the 6 stage ripple counter above , ( see figure 10-10 in Schaums for Nand gate connections ) what combination of FF outputs ( connected to the nand gate input ) would be required to make a mod 9, mod 22 and mod 29 up counter ? Mod 9 ______________ mod 22_____________ mod 29 ______________ d) What would the status of the four output bits ( i.e. bits A, B ,C and D ) of the 4 stage ripple up counter be after clock pulses 1 – 13 ?? ( assume the counter is reset to 0000 at time 0, just before clock pulse 1 ) Note output A is least significant bit. CLK A B C D 0 0 0 0 0 1 2 3 4 5 6 7 8 9 CLK A B C D 10 11 12 13 2.) Draw the schematic diagram for a serial J-K FF type counter circuit ( similar to Fig 10-10 in Schaums ) that will divide a 64 kHz square wave signal applied to the clock input of FF1 into an output square wave of 1 kHz . Assume an active high, positive edge trigger FF. 3.) For a 6 bit (6 stage ) binary serial up counter circuit, what will be the output count after 19 ,37 and 79 input pulses to the clock input ? (after 19 ) ___________ (after 37 ) _______________ after (79) _______________ Repeat the above for a 6 bit serial binary down counter . After 28 pulses _________ after 44 pulses____________ after 81 __________ 4.) Consider a simple series connected , 6 stage J K Flip Flop ripple down counter circuit Assume an active high, positive edge trigger FF. ( similar to Fig 10-11 ) a) If the clock input signal is a 44 kHz square wave; then what will the output frequencies be at outputs Q1, Q2, Q3 , Q 4 , Q5 and Q6 ? b) F1=__________ F2 = _________ F3 = _____________ F4= ____________F5=__________F6=___________ b) If a 7th and 8th flip flop stage are cascaded to this counter, what will the frequencies be at Q7 and Q8 ? F7 = _____________ F8 = _________________ c) If the output of a nand gate were connected to all of the active low reset pins on each FF in Fig 10-11, what combination of Q outputs ( connected to the nand gate input ) would be required to make a mod 1 9, mod 42 and mod 125 up counter ? Mod 19 ______________ mod 42_____________ mod 125 ______________ d) What would the status of the down counter’s six output bits ( i.e. bits A, B ,C, D,E and F) of the 6 stage ripple down counter be after clock pulses 1 – 10 ?? ( assume the counter is reset to 0000 at time 0, just before clock pulse 1 ) Note output A is least significant bit. CLK A B C D E F 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 10 7.) For a 5 bit parallel up counter circuit, ( similar to parallel counter in Fig 10-6 ) determine the status of output bits A – E for the corresponding clock pulses. Assume the counter was reset to 00000 just before clock pulse 1 is applied . CLK A B C D E 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 10 8.) Repeat # 7 above for a parallel 5 bit down counter circuit . CLK A B C D E 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 10 9.) Sketch the circuit diagrams for (a) a synchronous 4 bit, mod 11 parallel up counter and (b) a synchronous 4 bit mod 14 parallel down counter . Be sure to show nand gate connections to the Reset pins and the clock connections. (a) (b) 10.) (a) For a 4 bit serial shift- right register circuit ( refer to Fig 11-2 in Schaums ) fill out the truth table for the binary values that appear in the register slots A,B C, and D with respect to each of the clock pulses that occur in timeframes T1- T14 . Note that the shift register has active high serial data input pin, is level triggered, and has an active low Reset pin. Assume the register is Reset to 0000 at time T0 . Time T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 Clk 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Re 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 Serial_in 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 A 0 B 0 C 0 D 0 (b) Repeat the above truth table for a 4 bit serial shift left register : Time T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 Clk 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Re 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 Serial_in 1 0 1 0 1 0 1 1 1 0 0 1 1 0 1 A 0 B 0 C 0 D 0 11.) (a) For a 4 bit parallel shift right register circuit ( refer to Fig 11-5 in Schaums ) , fill out the truth table for the data outputs A, B, C and D corresponding to the clock pulses that occur in timeframes T1- T14 . Assume that the data outputs are Reset to 0000 in timeframe T0 and the parallel register has active high data input pins ( inputs a, b, c and d ) and active low Reset pin . Also Note that data inputs a-d are asynchronous and that this is a re-circulating ( i.e. wrap around ) type of parallel register . Assume output bit A and input bit a are the least significant bits . Also note that an asynchronous parallel 4 bit data input loading occurs at times T1 and T8 and T13. Time T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 Clk 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 RE 0 1 1 1 1 1 1 0 1 1 1 1 0 1 1 1 a 1 0 0 b 0 1 1 c 1 1 1 d 0 1 1 A 0 B 0 C 0 D 0 (b) Repeat part (a) above for a parallel shift left register : Time T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 Clk 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 RE 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 a 1 0 1 b 0 1 1 c 1 1 0 d 1 0 0 A 0 B 0 C 0 D 0 12.) For a universal shift register circuit, ( refer to Fig 11-8 in Schaums ) fill in the truth table for the binary outputs in register A – D . Assume the register is Reset to 0000 just before clock pulse 1 and that the universal register is in the mode of operation stated in the left most column. Assume the serial input data in parallel load inputs ad arrives just before the clock pulse arrives and that the register has active high data inputs. Also note that this is NOT a wrap around type register .( i.e. the data does NOT recirculate through register ) D_L = serial data input, shift left D_R = serial data input, shift right PAR = overriding parallel data load for input word d c b a Mode Re Clk D_L D_R a b c d A B C D Time Reset 0 1 X X X X X X 0 0 0 0 T0 PAR 1 1 0 1 T1 D_L 1 0 T2 D_L 1 1 T3 D_L 0 1 T4 PAR 0 0 1 0 T5 D_R 0 0 T6 D_R 0 1 T7 D_R 1 1 T8 D_R 1 0 T9 Reset T10 PAR 1 0 1 1 0 T11 D_L 1 1 T12 D_R 0 0 T13 D_R 0 0 T14 D_R 1 1 T15 D_L 1 1 T16 D_L 1 0 T17 Reset 0 T18

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