module FSM_tb;

reg KEY0, SW0, SW1, SW2, SW3, SW4;
wire [2:0] state;
wire [1:0] Z;

FSM uut(
.KEY0(KEY0),
.SW0(SW0),
.SW1(SW1),
.SW2(SW2),
.SW3(SW3),
.SW4(SW4),
.state(state),
.Z(Z)
);

initial begin
// First test case:
// SW0 = 1; SW1 = 0; SW2 = 0; SW3 = 0; SW4 = 0; KEY0 = 0; #10;
// SW0 = 0; SW1 = 1; SW2 = 0; SW3 = 0; SW4 = 0; #10;
// SW0 = 0; SW1 = 0; SW2 = 1; SW3 = 0; SW4 = 0; #10;
// SW0 = 0; SW1 = 0; SW2 = 0; SW3 = 1; SW4 = 0; #10;
// SW0 = 0; SW1 = 0; SW2 = 1; SW3 = 0; SW4 = 0; #10;
// #5;
// SW0 = 1; SW1 = 0; SW2 = 0; SW3 = 0; SW4 = 0; #10;

// Second test case:
SW0 = 1; SW1 = 0; SW2 = 0; SW3 = 0; SW4 = 0; KEY0 = 0; #10;
SW0 = 0; SW1 = 0; SW2 = 1; SW3 = 0; SW4 = 0; #10;
SW0 = 0; SW1 = 1; SW2 = 0; SW3 = 0; SW4 = 0; #10;
SW0 = 0; SW1 = 0; SW2 = 1; SW3 = 0; SW4 = 0; #10;
SW0 = 0; SW1 = 0; SW2 = 0; SW3 = 0; SW4 = 1; #10;
SW0 = 0; SW1 = 0; SW2 = 1; SW3 = 0; SW4 = 0; #10;
SW0 = 0; SW1 = 0; SW2 = 0; SW3 = 1; SW4 = 0; #10;
SW0 = 0; SW1 = 0; SW2 = 1; SW3 = 0; SW4 = 0; #10;
SW0 = 0; SW1 = 0; SW2 = 1; SW3 = 0; SW4 = 0; #10;
SW0 = 0; SW1 = 0; SW2 = 0; SW3 = 1; SW4 = 0; #10;
SW0 = 0; SW1 = 0; SW2 = 0; SW3 = 0; SW4 = 1; #10;
SW0 = 0; SW1 = 1; SW2 = 0; SW3 = 0; SW4 = 0; #10;
SW0 = 0; SW1 = 0; SW2 = 1; SW3 = 0; SW4 = 0; #10;
SW0 = 0; SW1 = 0; SW2 = 0; SW3 = 1; SW4 = 0; #10;
SW0 = 0; SW1 = 0; SW2 = 0; SW3 = 0; SW4 = 1; #10;
SW0 = 0; SW1 = 1; SW2 = 0; SW3 = 0; SW4 = 0; #10;
SW0 = 0; SW1 = 0; SW2 = 1; SW3 = 0; SW4 = 0; #10;
SW0 = 0; SW1 = 0; SW2 = 0; SW3 = 1; SW4 = 0; #10;
SW0 = 0; SW1 = 0; SW2 = 0; SW3 = 0; SW4 = 1; #10;
SW0 = 0; SW1 = 0; SW2 = 0; SW3 = 0; SW4 = 1; #10;

end

always begin
KEY0 = ~KEY0; #5;
end

endmodule

Question 1 Consider the impulse response and input signal xn]=aun...