module ALU_tb;

// inputs
reg [3:0] aluin_a;
reg [3:0] aluin_b;
reg [3:0] OPCODE;
reg    Cin;

// outputs
wire [3:0] alu_out;
wire Cout;
wire OF;

// ALU instance
ALU uut (
         .aluin_a(aluin_a),
         .aluin_b(aluin_b),
         .OPCODE(OPCODE),
         .Cin(Cin),
         .alu_out(alu_out),
         .Cout(Cout),
         .OF(OF)
         );

initial begin
   OPCODE = 0; // add
   aluin_a = 4'b0110; // signed 6, unsigned 6
   aluin_b = 4'b0011; // signed 3, unsigned 3
Cin = 1'b1; #100; // cin = 1
// Expected: result = 1001 (unsigned 9, Cout = 0; signed -7, OF = 1)

aluin_a = 4'b1111; // signed -1, unsigned 15
   aluin_b = 4'b0001; // signed 1, unsigned 1
Cin = 1'b0; #100; // cin = 0
// Expected: result = 0000 (unsigned 0, Cout = 1; signed 0, OF = 0)

aluin_a = 4'b1001; // signed -7, unsigned 9
   aluin_b = 4'b0110; // signed 6, unsigned 6
Cin = 1'b1; # 100; // cin = 1
// Expected: result = 1111 (unsigned 15, Cout = 0; signed -1, OF = 0)

aluin_a = 4'b0111; // signed 7, unsigned 7
   aluin_b = 4'b0001; // signed 1, unsigned 1
Cin = 1'b0; # 100; // cin = 0
// Expected: result = 1000 (unsigned 8, Cout = 0; signed -8, OF = 1)

aluin_a = 4'b1001; // signed -7, unsigned 9
   aluin_b = 4'b1100; // signed -4, unsigned 12
Cin = 1'b0; # 100; // cin = 0
// Expected: result = 0101 (unsigned 5, Cout = 1; signed 5, OF = 1)

aluin_a = 4'b1111; // signed -1, unsigned 15
   aluin_b = 4'b0000; // signed 0, unsigned 0
Cin = 1'b1; # 100; // cin = 1
// Expected: result = 1111 (unsigned 15, Cout = 0; signed -1, OF = 0)

aluin_a = 4'b1000; // signed -8, unsigned 8
   aluin_b = 4'b1111; // signed -1, unsigned 15
Cin = 1'b1; # 100; // cin = 1
// Expected: result = 0111 (unsigned 7, Cout = 1; signed 7, OF = 1)

Objective: Develop Verilog code using top down design. Lab Goal: F...