 # Your data: Put down your data in the following. Q2  = 7k&Ome...

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Your data: Put down your data in the following. Q2  = 7kΩ  7 ≠ 0 0kΩ  7 = 0 Your RD = ______ k e.g. X7 = 0 and so RD = 10 k Q9  = 6kΩ  6 ≠ 0 0kΩ  6 = 0 Your R1 = ______ k e.g. X6 = 5 and so R1 = 5 k SECTION A: Question 1 (8 marks) Consider the circuit in Figure Q1. Given R1 = 2 kW, R2 = 2 kW, R3 = 4 kW, R4 = 1 kW. The diodes D1 and D2 are assumed to have Vg = 0.7 V. (a) Assume that D1 is ON and D2 is OFF, determine the voltages VA, VB and current ID1. DQbbrreeaakk N breabkroeuatkout +9V ID2 ID1 VB VA Question 2 (6 marks) Figure Q2 shows a NMOS common-source amplifier circuit. The NMOS transistor parameters are: VTN = +1.0 V, Kn = 0.5 mA/V2 and l = 0. Given: VDD = +8 V, VGG = +2 V, RG = 3 k and your RD.  = 7k if your 7 ≠ 0 10 k if your7 = 0 Remark: You must use your own RD to finish this assignment. (a) Assume that the NMOS is biased in the saturation region. Find the Q-point parameters: IDQ, VGSQ, VDSQ. (5 marks) (b) Show your assumption is correct. (1 marks) Figure Q2 Question 3 (4 marks) A 6-bit digital-ramp A-D converter has a range of [0, +12V]. (a) What is the step size D of this converter? (1 mark) (b) State in binary form the final digital value that this A-D produces for an input voltage of +8.4V. Show all your calculations. + VDS _ + VGS _ ID RD = _______ k (c) Given the clock period is 1 μs, what is the maximum conversion time taken for this A-D converter? (1 mark) Question 4 (6 marks) A circuit is constructed from three flip-flops, as shown in Figure Q4, and outputs are taken from the Q output of each flip-flop. The initial values of these outputs are QA = 0, QB = 1, QC = 1 as shown. The flip-flops are all clocked from a common clock signal. Figure Q4 What will be the outputs after the receipt of four clock pulses? Clock JA KA QA JB KB QB JC KC QC Start 1 1 0 0 1 1 1 0 1 1 2 3 4 QA = 0 QB = 1 QC = 1 Question 5 (6 marks) Consider the circuit in Figure Q5. Assume that the op amp is ideal. (a) Using the phasor to prove that the voltage gain transfer function H(f) = Vout/Vin is given by 1 2 ( / ) / ( ) 1 2 1 j f L R R R H f + p = − (4 marks) (b) How does H(f) change with frequency f increasing from 0 to infinity? (2 marks) Figure Q5 SECTION B: Question 6 (20 marks) A sequential machine will be designed to control the sequence of a lighting system. There will be two inputs A and B, and three outputs R, S and T. A state-transition diagram of this machine is shown in Figure Q6(a). Figure Q6(a) (a) In your answer book complete a copy of the state-table shown in Figure Q6(b). Present State Inputs AB Outputs 00 01 10 11 R S T a b c d Next state Figure Q6(b) (6 marks) (b) The partially completed state-assignment table for this system is shown in Figure Q6(c). The combination CD represents the present state and EF represents the next state, i.e. “state a” is assigned 00, “state b” 01 etc. In your answer construct a table which shows the input columns ABCD and has just the completed output columns for E, F and S. (4 marks) Inputs Present state Next state Output A B C D E F R S T 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 0 0 1 0 0 1 1 0 0 0 1 0 0 1 0 0 1 0 1 1 0 0 1 1 0 0 1 0 1 1 1 0 0 1 0 0 0 1 0 1 0 0 1 1 0 1 0 1 0 0 1 1 0 1 1 0 0 1 1 0 0 1 0 1 1 0 1 1 0 1 1 1 0 0 1 1 1 1 1 0 0 Figure Q6(c) (c) Use the Karnaugh map to find simplified Boolean expressions for R. (2 marks) (d) Use two positive edge-triggered JK-type flip-flops (inputs J1 K1, J2, K2) to implement this sequential machine. Write down the Boolean expression for J1 K1, J2 and K2 in terms of A, B, C and D. (8 marks) Question 7 (20 marks) Figure Q7 (a) Consider the BJT circuit in Figure Q7. Let R1 = 7 k, R2 = 3 k, Vcc = +10 V. Assume that VBE(on) = 0.7 V, b = 100, and VA = ¥. You can assume that the impedances of capacitors C1, C2 and C3 are negligible in the operating frequency. Given the Q-point parameters are ICQ = 2.50 mA and VCEQ = 6.0 V. (i) What is the operating mode of the BJT? Explain your answer. (1 mark) (ii) Find the values of resistors RC and RE. (6 marks) (b) Draw the small-signal equivalent circuit of Figure Q7. (2 marks) (c) Find the small-signal voltage gain of the circuit. IC + VCE + _ VBE _

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