`timescale 1ns / 1ps
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// Company:
// Engineer:
//
// Create Date:
// Design Name:
// Module Name: fsm
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
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module FSM(nickel,dime,quarter,coin_ret,clk,init,gum,apple,yogurt,disp_item,crdl,crdr,change);
input nickel,dime,quarter,gum,apple,yogurt,clk,init,coin_ret;
output reg [6:0]disp_item,crdl,crdr;
output reg [2:0] change;
reg [2:0] state,next_state;

parameter Zero=0, //these are the states of the FSM
Five = 1,
Ten = 2,
Fifteen = 3,
Twenty = 4,
TwentyFive = 5;

always @(posedge clk) begin
if ((nickel&&dime)||(dime&&quarter)||(quarter&&nickel)||(nickel&&dime&&quarter)||(gum&&apple)||(apple&&yogurt)||(yogurt&&gum)||(gum&&apple&&yogurt))
next_state=Zero;

if (init)
next_state=Zero;

state=next_state;
case (state)
Zero: begin
crdl=7'd0;
crdr=7'd0;
if (nickel)
next_state=Five;
if (dime)
next_state=Ten;
if (quarter)
next_state=TwentyFive;
end
Five: begin
crdl=7'd0; //7 segment display is in the order of 0123456 i.e segA corresponds to MSB
crdr=7'b1011011

2 Problem 1 (20 pts) Given: Î²=100, VBE = 0.64, VA = ï‚¥ VCC = +...